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mt9f002: 1/2.3-inch 14 mp cmos digital image sensor features mt9f002 ds rev. h pub. 6/15 en 1 ?semiconductor components industries, llc 2015, 1/2.3-inch 14 mp cmos digital image sensor mt9f002 data sheet, rev. h for the latest data sheet, please visit: www.onsemi.com features ? 1.4 ? m pixel with on semiconductor a-pix? technology ? simple two-wire serial interface ? auto black level calibration ? full hd support at 60 fps for maximum video performance ? 20 percent extra image array area in full hd to enable electronic image stabilization (eis). ? support for external mechanical shutter ? support for external led or xenon flash ? high frame rate preview mode with arbitrary down- size scaling from maximum resolution ? programmable controls: gain, horizontal and vertical blanking, frame size/rate, exposure, left?right and top?bottom image reversal, window size, and panning ? data interfaces: parallel or four-lane serial high- speed pixel interface (hispi?) differential signaling (slvs) ? on-chip phase-locked loop (pll) oscillator ? bayer pattern downsize scaler applications ? digital video cameras ? digital still cameras general description the on semiconductor mt9f002 is a 1/2.3-inch cmos active-pixel digital imaging sensor with an active pixel array of 4608h x 3288v (4640h x 3320v including border pixels). it can support 14-megapixel (4384h x 3288v) digital still images and a 1080p plus additional 20 percent pixels for electronic image stabi- lization (4608h x 2592v) in digital video mode. the mt9f002 sensor is progra mmable through a simple two-wire serial interface, and has low power consump- tion. table 1: key performance parameters parameter value optical format 1/2.3-inch (4:3) active pixels and imager size ? 4608h x 3288v: (entire array): 6.451mm (h) x 4.603mm (v), 7.925mm diagonal ? 4384h x 3288v (4:3, still mode): 6.138mm (h) x 4.603mm (v), 7.672mm diagonal ? 4608h x 2592v (16:9, video mode): 6.451mm (h) x 3.629mm (v), 7.402mm diagonal pixel size 1.4 ? m x 1.4 ? m chief ray angle 0, 11.4, and 25 color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) with global reset release (grr) input clock frequency 2C64 mhz maxi- mum data rate parallel 96 mp/s at 96 mhz pixclk hispi (4-lane) 700 mbps/lane frame rate 14m resolution (4384h x 3288v) programmable up to 13.7 fps for hispi i/f, 6.3 fps for parallel i/f preview vga mode ? 30 fps with binning ? 60 fps with skip2bin2 1080p mode: ? 60 fps using hispi interface 2304h x 1296v (1080p +20%eis) ? 30 fps using parallel interface 2256h x 1268v (1080p +17%eis) adc resolution 12-bit, on-chip responsivity 0.724 v/lux-sec (550nm) dynamic range 65.3 db snr max 35.5 db supply voltage i/o digital 1.7C1.9 v (1.8 v nominal) or 2.4C3.1 v (2.8 v nominal) digital 1.7C1.9 v (1.8 v nominal) analog 2.7C3.1 v (2.8 v nominal) hispi phy hispi i/o (slvs) hispi i/o (hivcm) 1.7C1.9 v (1.8 v nominal) 0.3 - 0.9 v (0.4 or 0.8 v nominal) 1.7C1.9 v (1.8 v nominal) power con- sump- tion full resolution 13.65 fps (hispi serial i/f, 12-bit) 724 mw 1080p60 (hispi serial i/f, 10-bit) xybin2: 596 mw 1080p30 (hispi serial i/f, 10-bit) xybin2: 443 mw package 48-pin ilcc (10 mm x 10 mm) and bare die operating temperature C30c to +70c (at junction)
mt9f002 ds rev. h pub. 6/15 en 2 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description MT9F002I12STCV-DP rgb, 0deg cra, hispi, ilcc package drypack, protective film mt9f002i12-n4000-dp rgb, 12deg cra, hispi, ilcc package drypack, protective film mt9f002i12stcvd3-gevk 0deg cra, hispi, demo kit mt9f002i12stcvh-gevb 0deg cra, hispi, head board mt9f002i12-n4000d-gevk 12deg cra, hispi, demo kit mt9f002i12-n4000h-gevb 12deg cra, hispi, head board
mt9f002 ds rev. h pub. 6/15 en 3 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 hispi physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 comparison of slvs and hivcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 programming restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 control of the signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 sensor readout configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 power mode contexts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 sensor core digital data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
mt9f002 ds rev. h pub. 6/15 en 4 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2: data flow diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: pixel color pattern detail (top ri ght corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: high-resolution still image capture + full hd video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: typical configuration: serial fo ur-lane hispi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: typical configuration: parallel pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7: 48-pin ilcc hispi packag e pinout diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 8: data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 9: steaming vs. packetized transmis sion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 10: hispi transmitter and receiver interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 12: block diagram of dll timing ad justment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: delaying the clock_lane with re spect to data_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 14: delaying data_lane with respect to the clock_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: spatial illustration of image readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 16: pixel data timing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 17: frame timing and fv/lv signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 18: single read from random locati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 19: single read from current locati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 20: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 21: sequential read, start from current location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 22: single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 23: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 24: effect of limiter on the data path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 25: timing of data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 26: mt9f002 system states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 27: clocking configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 28: effect of horizontal mirror on readout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 29: effect of vertical flip on re adout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 30: effect of x_od d_inc=3 on readout sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 31: effect of x_od d_inc=7 on readout sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 32: pixel readout (no subsampling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 33: pixel readout (x_odd_inc=3, y_odd _inc=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 34: pixel readout (x_odd_inc=1, y_odd _inc=3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 35: pixel readout (x_odd_inc=3, y_odd _inc=3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 36: pixel readout (x_odd_inc=7, y_odd _inc=7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 37: pixel readout (x_odd_inc=7, y_odd _inc=15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 38: pixel readout (x_odd_inc=7, y_odd _inc=31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 39: pixel binning and summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 40: bayer resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 41: results of resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 42: analog gain stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 43: xenon flash enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 44: led flash enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 45: led flash enabled following forc ed restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 46: overview of global reset sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 47: entering and leaving a global re set sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 48: controlling the reset and integration phases of the gl obal reset sequence . . . . . . . . . . . . . . . . . . . .59 figure 49: control of the electromechanica l shutter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 50: controlling the shutter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 51: using flash with global reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 52: global reset bulb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 53: entering soft standby during a global reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 54: slave mode grr timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 55: slave mode hispi output (ers to grr transition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 56: 100% color bars test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
mt9f002 ds rev. h pub. 6/15 en 5 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor list of figures figure 57: fade-to-gray color bar test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 58: walking 1s 12-b it pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 59: walking 1s 10-b it pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 60: walking 1s 8-bit patt ern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 61: test cursor behavior with image orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 62: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 63: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 64: hard standby and hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 65: soft standby and soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 66: quantum efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 67: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 68: i/o timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 figure 69: single-ended and differential sign als . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 70: dc test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 71: clock-to-data skew timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 72: differential skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 73: transmitter eye mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 74: clock duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 figure 75: clock jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 figure 76: 48-pin ilcc package outline drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
mt9f002 ds rev. h pub. 6/15 en 6 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 4: slvs and hivcm comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 5: common sensor readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 6: definitions for programming rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 7: output enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 8: configuration of the pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 9: reset_bar and pll in system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 10: signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 11: streaming/standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 12: trigger control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 13: pll parameter range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 14: minimum row time and blanking numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 15: minimum frame time and blanking numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 16: fine_integration_time limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 17: fine_correction values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 18: power mode contexts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 19: recommended register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 20: test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 21: hispi test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 22: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table 23: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 24: 11.4 chief ray angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 table 25: 25 chief ray angle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 table 26: cra value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 table 27: dc electrical definitions and char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 28: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 29: two-wire serial register interface electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 table 30: two-wire serial register interface timing specificatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 table 31: i/o parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 32: i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 33: power supply and operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 34: slvs electrical dc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 35: slvs electrical timing specificat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 36: hivcm power supply and operating temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 37: hivcm electrical voltage and impedance specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 table 38: hivcm electrical ac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
mt9f002 ds rev. h pub. 6/15 en 7 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor general description general description the mt9f002 digital image sensor features on semiconductor?s breakthrough low-noise cmos imaging technology that ac hieves near-ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. when operated in its default 4:3 still-mode , the sensor generates a full resolution (4384x3288)image at 13 frames per second (fps) using the hispi serial interface. an on-chip analog-to-digital converter (adc) generates a 12-bit value for each pixel. functional overview the mt9f002 is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) to generate all internal clocks from a single master input clock running between 2 and 64 mhz. the maximum output pixel rate is 220 mp/s for serial hispi i/f and 96 mp/s for parallel i/f, corre- sponding to a pixel clock rate of 220 mhz and 96 mhz, respectively. a block diagram of the sensor is shown in figure 1. figure 1: block diagram the core of the sensor is a 14mp active-pix el array. the timing and control circuitry sequences through the rows of the array, rese tting and then reading each row in turn. in the time interval between resetting a row and re ading that row, the pixels in the row inte- grate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chai n (providing offset correction and gain), and then through an adc. the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). the pixel array contains optically active and light-shielded (?dark?) pixels. the dark pixels are used to provide data for on-chip offset-correction algorithms (?black level? control). pll timing and control registers pixel array column amplifiers column amplifiers row drivers voltage reference black level correction scaler limiter output buffer/fifo lens shading correction digital gain data pedestal i 2 c extclk analog core core data path test pattern generator parallel i/o: pixclk fv, lv, d out [11:0] serial hispi: slvsc p/n, slvs[3:0] p/n output data path pga pga adc adc 12 bits 12 bits 12 bits 12 bits
mt9f002 ds rev. h pub. 6/15 en 8 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor functional overview the image black level is calibrated to compen sate for analog offset and ensure that the adc range is utilized well. it also reduces row noise in the image. the black level in the output image involves fine digital correction and addition of data pedestal (42 lsb for 10-bit adc, 168 lsb for 12-bit adc) figure 2: data flow diagram the sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers can be accessed through a two-wire serial interface. the output from the sensor is a bayer pattern ; alternate rows are a sequence of either green and red pixels or blue and green pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. the control registers, timing and control, and digital processing functions shown in figure 1 on page 7 are partitioned into three logical parts: ? a sensor core that provides array control and data path corrections. the output of the sensor core is a 12-bit parallel pixel data stream qualified by an output data clock (pixclk), together with line_valid (lv) and frame_valid (fv) signals or a 4-lane serial high-speed pixel interface (hispi). ? a digital shading correction block to comp ensate for color/brightness shading intro- duced by the lens or chief ray angle (cra) curve mismatch. ? additional functionality is provided. this includes a horizontal and vertical image scaler, a limiter, an output fifo, and a serializer. the output fifo is present to prevent data bursts by keeping the data rate continuous. programmable slew rates are al so available to reduce the e ffect of electromagnetic inter- ference from the output interface. a flash output signal is provided to allow an external xenon or led light source to synchronize with the sensor exposure time. additional i/o signals support the provision of an external mechanical shutter. pixel array the sensor core uses a bayer color pattern, as shown in figure 3. the even-numbered rows contain green and red pixels; odd-numbered rows contain blue and green pixels. even-numbered columns contain green and blue pixels; odd-numbered columns contain red and green pixels. lens shading correction black level calibration adc analog gain dac analog analog offset calibration digital gain data pedestal pixel output digital 12-bit
mt9f002 ds rev. h pub. 6/15 en 9 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor functional overview figure 3: pixel color pattern detail (top right corner) figure 4: high-resolution still image capture + full hd video black pixels column readout direction . . . ... row readout direction gr b gr r gb r gr b gr r gb r first clear active pixel (col 114, row 106) gr b gr
mt9f002 ds rev. h pub. 6/15 en 10 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor operating modes operating modes by default, the mt9f002 powers up with th e serial pixel data interface enabled. the sensor can operate in serial hispi or parallel mode. for low-noise operation, the mt9f002 requir es separate power supplies for analog and digital power. incoming digital and analog ground conductors should be placed in such a way that coupling between the two are mini mized. both power supply rails should also be routed in such a way that noise coupli ng between the two supplies and ground is minimized. caution on semiconductor does not recommend the use of inductance filters on the power supplies or output signals. figure 5: typical configuration: serial four-lane hispi interface notes: 1. all power supplies should be adequately de coupled. on semiconductor recommends having 1.0 ? f and 0.1 ? f decoupling capacitors for every power supply. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. the gpi pins can be statically pulled high or lo w and can be programmed to perform special func- tions (trigger/vd, oe_bar, s addr , standby) to be dynamically controlled. gpi pads can be left floating, when not used. 5. v pp , which is not shown in figure 5, is le ft unconnected during normal operation. v dd _io v dd _tx v dd _pll v dd v aa v dd v dd _tx v aa v aa _pix master clock (2C64 mhz) s data s clk reset_bar test extclk d gnd a gnd digital ground analog ground digital core power 1 hispi phy i/o power 1, 10 analog power 1 to controller from controller v dd _io v dd _pll pll power 1 digital i/o power 1 1.5k 2 1.5k 2, 3 analog power 1 v aa _pix slvsc_n slvsc_p slvs_0p slvs_0n slvs_1p slvs_1n slvs_2p slvs_2n slvs_3p slvs_3n flash shutter gpi[3:0] 4 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f v dd _ hi sp i
mt9f002 ds rev. h pub. 6/15 en 11 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor operating modes 6. the parallel interface output pads can be left unconnected when the serial output interface is used. 7. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. check the mt9f00 2 demo headboard schematics for circuit recom- mendations. 8. test signals must be tied to d gnd for normal sensor operation. 9. on semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized. 10. for serial hispi hivcm mode, set register bit r0x306e[9] = 1 and v dd _tx = v dd _io = 1.8v. figure 6: typical configuration: parallel pixel data interface notes: 1. all power supplies should be adequately de coupled. on semiconductor recommends having 1.0 ? f and 0.1 ? f decoupling capacitors for every power supply. 2. on semiconductor recommends a resistor value of 1.5k ? , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. the gpi pins can be statically pulled high or lo w and can be programmed to perform special func- tions (trigger/vd, oe_bar, s addr , standby) to be dynamically controlled. gpi pads can be left floating, when not used. 5. v pp , which is not shown in figure 6, is le ft unconnected during normal operation. 6. the serial interface output pads can be left unco nnected when the parallel ou tput interface is used. 7. on semiconductor recommends that 0.1 ? f and 10 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. check the mt9f00 2 demo headboard schematics for circuit recom- mendations. 8. test signals must be tied to d gnd for normal sensor operation. v aa _pix v dd master clock (2C64 mhz) s data s clk reset_bar test flash frame_valid shutter d out [11:0] extclk d gnd a gnd digital ground analog ground digital core power 1 to controller parallel port from controller line_valid pixclk v dd _io gpi[3:0] 4 digital i/o power 1 1.5k 2 1.5k 2, 3 v dd _io v dd _pll v dd v aa v aa v aa _pix analog power 1 v dd _pll pll power 1 analog power 1 1.0 f 0.1 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f 0.1 f 1.0 f
mt9f002 ds rev. h pub. 6/15 en 12 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor operating modes 9. on semiconductor recommends that analog power planes are placed in a manner such that cou- pling with the digital power planes is minimized.
mt9f002 ds rev. h pub. 6/15 en 13 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor signal descriptions signal descriptions table 3 provides signal descriptions for mt9f002 die. for pad location and aperture information, refer to the mt9f002 die data sheet. table 3: signal descriptions signal type description extclk input master clock input, 2-64 mhz. reset_bar input asynchronous active low reset. when asserted, data output stops and all internal registers are restored to their factory default settings. s clk input serial clock for access to control and status registers. gpi[3:0] input general purpose inputs. after reset, these pads are powered-down by default; this means that it is not necessary to bond to these pads. any of these pads can be programmed (through register r0x3026) to provide hardware control of the standby, output enable, s addr select, shutter trigger or slave mode trigger (vd) function. can be left floating if not used. test input enable manufacturing test modes. tie to d gnd for normal sensor operation. s data i/o serial data from reads and writes to control and status registers. v pp supply disconnect pad for normal operation. power supply used to program one-time programmable (otp) memory. manufacturing use only. v dd _hispi supply hispi phy power supply. digital power supply for the hispi serial data interface. this should be tied to v dd . v dd _tx supply digital power supply for the hispi i/o. for hispi slvs mode, set register bit r0x306e[9] = 0 (default), and vdd_tx to 0.4v. for hispi hivcm mode, set register bit r0x306e[9] = 1, and vdd_tx = vdd_io. v aa supply analog power supply. v aa _pix supply analog power supply for the pixel array. a gnd supply analog ground. v dd supply digital power supply. v dd _io supply i/o power supply. d gnd supply common ground for digital and i/o. v dd _pll supply pll power supply. slvs_0p output lane 1 differential hispi (slvs) serial data (positive). qualified by the slvs serial clock. slvs_0n output lane 1 differential hispi (slvs) serial data (negative). qualified by the slvs serial clock. slvs_1p output lane 2 differential hispi (slvs) serial data (positive). qualified by the slvs serial clock. slvs_1n output lane 2 differential hispi (slvs) serial data (negative). qualified by the slvs serial clock. slvs_2p output lane 3 differential hispi (slvs) serial data (positive). qualified by the slvs serial clock. slvs_2n output lane 3 differential hispi (slvs) serial data (negative). qualified by the slvs serial clock. slvs_3p output lane 4 differential hispi (slvs) serial data (positive). qualified by the slvs serial clock.
mt9f002 ds rev. h pub. 6/15 en 14 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor signal descriptions figure 7: 48-pin ilcc hispi package pinout diagram slvs_3n output lane 4 differential hispi (slvs) serial data (negative). qualified by the slvs serial clock. slvs_cp output differential hispi (slvs) serial clock (positive). qualified by the slvs serial clock. slvs_cn output differential hispi (slvs) serial clock (negative). qualified by the slvs serial clock. line_valid output line_valid (lv) output . qualified by pixclk. frame_valid output frame_valid (fv) output. qualified by pixclk. d out [11:0] output parallel pixel data output. qualified by pixclk. pixclk output pixel clock. used to qualify the lv, fv, and d out [11:0] outputs. flash output flash output. synchronization pulse for external light source. can be left floating if not used. shutter output control for external mechanical shutter. can be left floating if not used. table 3: signal descriptions (continued) signal type description 1 2 3 4 5 6 48474645 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 a gnd v aa nc v aa a gnd v aa _pix v aa _pix nc nc v aa a gnd v dd _hispi v dd _io d gnd v dd extclk v dd d gnd v dd _io s data sclk test reset_bar v dd d gnd v dd _io gpi0 gpi1 gpi2 gpi3 shutter flash v dd _pll vpp v dd _tx slvs_0n slvs_0p slvs_1n slvs_1p slvs_cn slvs_cp slvs_2n slvs_2p slvs_3n slvs_3p d gnd nc d gnd
mt9f002 ds rev. h pub. 6/15 en 15 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor output data format output data format pixel data interface the mt9f002 reads data out of the pixel array in a progressive scan over a high speed serial data interface, or parallel data interface. raw8, raw10, and raw12 image data formats are supported. figure 8: data formats high speed serial pixel data interface the high speed serial pixel (hispi) tm interface uses four data and one clock low voltage differential signaling (slvs) outputs. ?slvs_cp ?slvs_cn ?slvs_0p ?slvs_0n ?slvs_1p ?slvs_1n ?slvs_2p ?slvs_2n ?slvs_3p ?slvs_3n the hispi interface supports the following protocols: streaming-s and packetized-sp. the streaming protocol conforms to a standa rd video application where each line of active or intra-frame bl anking provided by the sensor is transmitted at the same length. the packetized protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. hispi streaming mode protocol layer the protocol layer is position ed between the output data path of the sensor and the physical layer. the main functions of the protocol layer are generating sync codes, formatting pixel data, inserting horizontal/v ertical blanking codes, and distributing pixel data over defined data lanes. the hispi interface can only be configured when the sensor is in standby. this includes configuring the interface to transmit across 1, 2, or all 4 data lanes. d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 raw12 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x raw10 d7 d6 d5 d4 d3 d2 d1 d0 x x x x raw8 cd
mt9f002 ds rev. h pub. 6/15 en 16 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor hispi physical layer protocol fundamentals referring to figure 9, it can be seen that a sync code is inserted in the serial data stream prior to each line of image data. the stream ing protocol will insert a sync code to transmit each active data line and vertical blanking lines. the packetized protocol will tr ansmit a sync code to note the start and end of each row. the packetized protocol uses sync a ?start of frame? (sof) sync code at the start of a frame and a ?start of line? (sol) sync code at the start of a line within the frame. the protocol will also transmit an ?end of frame? (eof) at the end of a frame and an ?end of line? (eol) sync code at the end of a row within the frame figure 9: steaming vs . packetized transmission note: see the high-speed serial pixel (hispi)? protocol specification v1.00.00 for hispi details. hispi physical layer the hispi physical layer is partitioned into bl ocks of four data lanes and an associated clock lane. any reference to the phy in the remainder of this document is referring to this minimum building block. the hispi phy uses a low voltage serial differential output. the hispi phy drivers use a simple current steering driver scheme with two outputs that are complementary to each other (v oa and v ob ). it is intended that these driver s be attached to short-length 100 ? differential interconnect to a receiver with a 100 ? termination. cl represents the total parasitic excess capacitance loading of the receiver and the interconnect. there are two standards: ? scalable low voltage serial (slvs) which has low amplitude and common-mode voltage (vcm) but scalable using an external supply. ? high vcm scalable serial interface (hivcm), which has larger scalable amplitude and a high common-mode voltage. ?
mt9f002 ds rev. h pub. 6/15 en 17 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor comparison of slvs and hivcm comparison of slvs and hivcm here is a comparison of the differences between slvs and hivcm. notes: 1. these are nominal values 2. power from load driving stage, digital/se rializer logic (vdd_hispi) not included. the hispi interface building block is a unidirectional differential serial interface with four data and one double data rate (ddr) cloc k lanes. the four data lanes are 90 degrees out of phase with the clock lanes. one clock for every four serial data lanes is provided for phase alignment across multiple lanes. figure 10 shows the configuration between the hispi transmitter and the receiver. figure 10: hispi transmitter and receiver interface block diagram the phy will serialize a 10-, 12-, 14- or 16-bit data word and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of clock. figure 11 shows bit transmission. in this example, the wo rd is transmitted in order of msb to lsb. the receiver latches data at the ri sing and falling edge of the clock. table 4: slvs and hivcm comparison parameter hivcm slvs typical differential amplitude 1 280mv 200mv typical common mode 1 0.9v 200mv typical power consumption 2 45mw 4mw transmission distance longer distance short distance lvds fpga receiver compatible yes no a camera containing the hispi transmitter a host (dsp) containing the hispi receiver data_p data_n data2_p data2_n data3_p data3_n data4_p data4_n clk_p clk_n tx phy0 rx phy0 data_p data_n data2_p data2_n data3_p data3_n data4_p data4_n clk_p clk_n
mt9f002 ds rev. h pub. 6/15 en 18 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor comparison of slvs and hivcm figure 11: timing diagram dll timing adjustment the specification includes a dll to compensate for differences in group delay for each data lane. the dll is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. once the dll has gained phase lock, each lane can be delayed in 1/8 unit interval (ui) steps. this additional delay allows the user to increase the setup or hold time at the rece iver circuits and can be used to compensate for skew introduced in pcb design. if the dll timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation. figure 12: block diagram of dll timing adjustment c p dn . . msb lsb txpost dp cn 1 ui txpre delay del0[2:0] delay del1[2:0] delay delay del3[2:0] delay del2[2:0] data_lane 0 data_lane 1 clock _lane 0 data_lane 2 data_lane 3 delclock[2:0]
mt9f002 ds rev. h pub. 6/15 en 19 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor comparison of slvs and hivcm figure 13: delaying the clock_lane with respect to data_lane figure 14: delaying data_lane with respect to the clock_lane note: see the high-speed serial pixel (hispi)? ph ysical layer specificatio n v2.00.00 for details. parallel pixel data interface mt9f002 image data is read out in a progressive scan. valid image data is surrounded by horizontal blanking and vertical blanking, as shown in figure 15. the amount of hori- zontal blanking and vertical blanking is pr ogrammable; lv is high during the shaded region of the figure. fv timing is described in the ?output data timing (parallel pixel data interface)?. datan (de ln = 000) cp ( delclock = 000) cp (delclock = 001) cp (delclock = 010) cp (de lclock = 011) cp ( delclock = 100) cp (d elcloc k = 1 01) c p (delclock = 110) cp ( delclock =111) increasing delclock_[2:0] increases clock delay 1 ui 1 ui t dllstep cp ( delclock = 000) datan (deln = 000) datan(deln = 001) datandeln = 010) datan(deln = 011) datan(deln = 100) datan(deln = 101) datan(deln = 110) datan(deln = 111) increasing deln_[2:0] increases data delay
mt9f002 ds rev. h pub. 6/15 en 20 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor comparison of slvs and hivcm figure 15: spatial illustration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 valid image horizontal blanking 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 vertical blanking vertical/horizontal blanking
mt9f002 ds rev. h pub. 6/15 en 21 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor comparison of slvs and hivcm output data timing (paralle l pixel data interface) mt9f002 output data is synchronized with the pixclk output. when lv is high, one pixel value is output on the 12-bit d out output every pixclk period. the pixel clock frequency can be determined based on the sensor's master input clock and internal pll configuration. the rising edges on the pixclk signal occurs one-half of a pixel clock period after transitions on lv, fv, and d out (see figure 16). this allows pixclk to be used as a clock to sample the data. pixclk is continuously enabled, even during the blanking period. the mt9f002 can be programme d to delay the pixclk edge relative to the d out transitions. this can be achieved by programming the corresponding bits in the row_speed register. figure 16: pixel data timing example figure 17: frame timing and fv/lv signals the sensor timing is shown in terms of pixel clock cycles (see figure 16 on page 21). the default settings for the on-chip pll generate a pixel arra y clock (vt_pix_clk) of 110 mhz and an output clock (op_pix_clk) of 55 mh z given a 24 mhz input clock to the mt9f002. equations for calculating the frame rate are given in ?frame rate control? on page 51. p 0 [11:0] p 1 [11:0] p 2 [11:0] p 3 [11:0] p 4 [11:0] p 5 p n-2 p n-1 [11:0] p n [11:0] valid image data blanking blanking lv pixclk d out [11:0] frame_valid line_valid pa q a a p q v
mt9f002 ds rev. h pub. 6/15 en 22 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor comparison of slvs and hivcm table 5: common sensor readout modes key readout modes output resolution aspect ratio dfov: 7.67 mm (%) subsampling mode frame rate adc effective bit-depth data rate (mbps/lane) 14m capture 4384h x 3288v (4:3) 100 n/a 13.7 12 660 1080p +20% eis (3mp) video 2304h x 1296v (16:9) 96 x: bin2 y: bin2 60 10 550 2304h x 1296v (16:9) 96 x: bin2 y: bin2 30 10 275 720p +20%eis (1.3mp) video 1536h x 864v (16:9) 64 x: bin2 y: bin2 60 10 550 1536h x 864v (16:9) 64 x: bin2 y: bin2 30 10 275 vga video (high quality) 1096h x 822v (4:3) 100 x: skip2bin2 y: bin4 60 10 550 evf1 - preview (low power) 1096h x 822v (4:3) 100 x: skip2bin2 y: bin4 30 10 275 evf2 - preview (low power) 1152h x 648v (16:9) 96 x: skip2bin2 y: bin4 30 10 275
mt9f002 ds rev. h pub. 6/15 en 23 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor two-wire serial register interface two-wire serial register interface the two-wire serial interface bus enables read /write access to control and status regis- ters within the mt9f002. the interface protocol uses a master/slave model in which a master controls one or more slave devices. th e sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and is used to synchronize trans- fers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd _io off-chip by a 1.5k ? resistor. either the slave or master device can drive s data low?the interface protocol determines which device is allowed to drive s data at any given time. the protocols described in the two-wire seri al interface specific ation allow the slave device to drive s clk low; the mt9f002 uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no-) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released wi th a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a ?repeated start? or ?restart? condition. stop condition a stop condition is defined as a low-to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for both the slave address/data direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the mt9f002 sensor are 0x20 (write address) and 0x21 (read address). alternative slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the saddr signal through the gpi pin.
mt9f002 ds rev. h pub. 6/15 en 24 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor two-wire serial register interface alternate slave addresses can also be programmed through the i2c_ids register (r0x31fc-31fd). note that this register needs to be unlocked through reset_regis- ter_lock_reg (r0x301a[3]) before is can be written to.. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the sclk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indi- cates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowl- edge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which the write should take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence . the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same wa y as with a write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the slave?s inte rnal register address is automatically incre- mented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
mt9f002 ds rev. h pub. 6/15 en 25 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor two-wire serial register interface single read from random location this sequence (figure 18) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates th e write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. the master termin ates the read by generating a no-acknowl- edge bit followed by a stop condition. figure 18 shows how the internal register address maintained by the mt9f002 is loaded and incremented as the sequence proceeds. figure 18: single read from random location single read from current location this sequence (figure 19) performs a read using the current value of the mt9f002 internal register address. the master terminates the read by generating a no-acknowl- edge bit followed by a stop condition. the figure shows two independent read sequences. figure 19: single read from current location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a
mt9f002 ds rev. h pub. 6/15 en 26 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor two-wire serial register interface sequential read, start from random location this sequence (figure 20) starts in the same way as the single read from random loca- tion (figure 18). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master genera tes an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 20: sequential read, start from random location sequential read, start from current location this sequence (figure 21) starts in the same way as the single read from current loca- tion (figure 19 on page 25). instead of gener ating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 21: sequential read, start from current location single write to random location this sequence (figure 22) begins with the ma ster generating a start condition. the slave address/data direction byte signals a writ e and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 22: single write to random location slave address 0 s sr a reg address[15:8] read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 read data read data m+l-2 m+l-1 m+l a p a a a a read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a reg address[7:0] a p previous reg address, n reg address, m m+1 a a write data
mt9f002 ds rev. h pub. 6/15 en 27 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor two-wire serial register interface sequential write, start at random location this sequence (figure 23) starts in the same way as the single write to random location (figure 22 on page 26). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master gene rates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the write is terminated by the master generating a stop condition. figure 23: sequential write, start at random location slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor programming restrictions mt9f002 ds rev. h pub. 6/15 en 28 ?semiconductor components industries, llc,2015. programming restrictions the following sections list programming rules that must be adhered to for correct opera- tion of the mt9f002. refer to the mt9f002 register reference document for register programming details. x address restrictions the minimum column address available for the sensor is 24. the maximum value is 4647. effect of scaler on legal range of output sizes when the scaler is enabled, it is necessary to adjust the values of x_output_size and y_output_size to match the image size ge nerated by the scaler. the mt9f002 will operate incorrectly if the x_output_size and y_output_size are significantly larger than the output image. to understand the reason for this, consider the situation where the sensor is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the number of pixels in each direction). this situation is shown in figure 24. figure 24: effect of limiter on the data path in figure 24, three different stages in the data path (see ?timing specifications? on page 71) are shown. the first stage is the output of the sensor core. the core is running at full resolution and x_output_size is set to ma tch the active array si ze. the lv signal is asserted once per row and remains asserted for n pixel times. the pixel_valid signal toggles with the same timing as lv, indicating that all pixels in the row are valid. the second stage is the output of the scaler, when the scaler is set to reduce the image size by one-half in each dimension. the effe ct of the scaler is to combine groups of pixels. therefore, the row time remains the same, but only half the pixels out of the scaler are valid. this is signaled by transi tions in pixel_valid. overall, pixel_valid is asserted for ( n /2) pixel times per row. table 6: definitions for programming rules name definition xskip xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3; xskip = 4 if x_odd_inc = 7 yskip yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3; yskip = 4 if y_odd_inc = 7; yskip = 8 if y_odd_inc = 15; yskip = 16 if y_odd_inc = 31; yskip = 32 if y_odd_inc = 63 core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line_valid scaler output: scaled to half size line_valid pixel_valid limiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1 line_valid pixel_valid pixel_valid
mt9f002 ds rev. h pub. 6/15 en 29 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor programming restrictions the third stage is the output of the limiter when the x_output_size is still set to match the active array size. because the scaler has reduced the amount of valid pixel data without reducing the row time, the limiter attempts to pad the row with ( n /2) additional pixels. if this has the effect of extending lv across th e whole of the horizontal blanking time, the mt9f002 will cease to generate output frames. a correct configuration is shown in figure 25, in addition to showing the x_output_size reduced to match the output size of the scaler . in this configuration, the output of the limiter does not extend lv. figure 25 also shows the effect of the output fifo, which forms the final stage in the data path. the output fifo merges the intermittent pixel data back into a contiguous stream. although not shown in this example, the outp ut fifo is also capable of operating with an output clock that is at a diffe rent frequency from its input clock. figure 25: timing of data path core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line_valid scaler output: scaled to half size line_valid pixel_valid limiter output: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 pixel_valid line_valid pixel_valid output fifo: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 line_valid pixel_valid
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor programming restrictions mt9f002 ds rev. h pub. 6/15 en 30 ?semiconductor components industries, llc,2015. output data timing the output fifo acts as a boundary between two clock domains. data is written to the fifo in the vt (video timing) clock domain. data is read out of the fifo in the op (output) clock domain. when the scaler is disabled, the data rate in the vt clock domain is constant and uniform during the active period of each pi xel array row readout. when the scaler is enabled, the data rate in the vt clock domain becomes intermittent, corresponding to the data reduction performed by the scaler. a key constraint when configuring the clock fo r the output fifo is that the frame rate out of the fifo must exactly match the frame rate into the fifo. when the scaler is disabled, this constraint can be met by imposi ng the rule that the row time on the serial data stream must be greater than or equal to the row time at the pixel array. the row time on the serial data stream is calculated from the x_output_size and the data_format (8, 10, or 12 bits per pixel), and must include the time taken in the serial data stream for start of frame/row, end of row/frame and checksum symbols. caution if this constraint is not met, the fifo will either underrun or overrun. fifo underrun or over- run is a fatal error condition that is signaled through the data path_status register (r0x306a). changing registers while streaming the following registers should only be repr ogrammed while the sensor is in software standby: ?vt_pix_clk_div ? vt_sys_clk_div ? pre_pll_clk_div ? pll_multiplier ? op_pix_clk_div ?op_sys_clk_div programming restrictions when using global reset interactions between the registers that co ntrol the global reset imposes some program- ming restrictions on the way in which they are used; these are discussed in "global reset" on page 58.
mt9f002 ds rev. h pub. 6/15 en 31 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor control of the signal interface control of the signal interface this section describes the operation of the signal interface in all functional modes. serial register interface the serial register interface uses these signals: ?s clk ?s data ?s addr (through the gpi pin) s clk is an input-only signal and must always be driven to a valid logic level for correct operation; if the driving device can place th is signal in high-z, an external pull-up resistor should be connected on this signal. s data is a bidirectional signal. an external pull-up resistor should be connected on this signal. s addr is a signal that can be optionally enable d and controlled by a gpi pin to select an alternate slave address. th ese slave addresses can also be programmed through r0x31fc. this interface is described in detail in ?two-wire serial register interface? on page 23. parallel pixel data interface the parallel pixel data interfac e uses these output-only signals: ?fv ?lv ?pixclk ?d out [11:0] the parallel pixel data interface is disabled by default at power up and after reset. it can be enabled by programming r0x301a. table 8 on page 32 shows the recommended settings. when the parallel pixel data interface is in us e, the serial data output signals can be left unconnected. set reset_register[12] to disable the serializer while in parallel output mode. output enable control when the parallel pixel data interface is en abled, its signals can be switched asynchro- nously between the driven and high-z under pin or register control, as shown in table 7. selection of a pin to use for the oe_n functi on is described in "general purpose inputs" on page 35. table 7: output enable control oe_n pin drive signals r0x301aCb[6] description disabled 0 interface high-z disabled 1 interface driven 1 0 interface high-z x1interfacedriven 0xinterfacedriven
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor control of the signal interface mt9f002 ds rev. h pub. 6/15 en 32 ?semiconductor components industries, llc,2015. configuration of the pixel data interface fields in r0x301a are used to configure the operation of the pixel data interface. the supported combinations are shown in table 8. table 8: configuration of the pixel data interface serializer disable r0x301 aCb[12] parallel enable r0x301aCb[7] standby end-of-frame r0x301aCb[4] description 0 0 1 power up default. serial pixel data interface and its clocks are enabled. transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 0 parallel pixel data interface, sensor core data output. serial pixel data interface and its clocks disabled to save power. transitions to soft standby are synchronized to the end of the current row readout on the parallel pixel data interface. 1 1 1 parallel pixel data interface, sensor core data output. serial pixel data interface and its clocks disabled to save power. transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface.
mt9f002 ds rev. h pub. 6/15 en 33 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor control of the signal interface system states the system states of the mt9f002 are repres ented as a state diagram in figure 26 and described in subsequent sections. the effect of reset_bar on the system state and the configuration of the pll in the different states are shown in table 9 on page 34. the sensor?s operation is broken down into three separate states: hardware standby, software standby, and streaming. the tran sition between these states might take a certain amount of clock cyc les as outlined in table 9. figure 26: mt9f002 system states powered off streaming powered on por =1 reset _bar transitions 1 -> 0 (asynchronous from any state ) initialization timeout two-wire serial interface write mode_select = 0 pll lock pll locked software reset initiated (synchronous from any state) wait for frame end software standby two-wire serial interface write mode_select = 1 two-wire serial interface write software_reset = 1 internal initialization hardware standby 2700 extclk cycles reset_bar = 0 por = 0 reset_bar = 1 pll not locked por active (only if por is on sensor) power supplies turned off (asychronous from any state) frame in progress
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor control of the signal interface mt9f002 ds rev. h pub. 6/15 en 34 ?semiconductor components industries, llc,2015. note: vco = voltage-controlled oscillator. power-on reset sequence when power is applied to the mt9f002, it enters a low-power hardware standby state. exit from this state is controlled by the later of two events: 1. the negation of the reset_bar input. 2. a timeout of the internal power-on reset circuit. it is possible to hold reset_bar permanently de-asserted and rely upon the internal power-on reset circuit. when reset_bar is asserted it asynchronous ly resets the sensor, truncating any frame that is in progress. when the sensor leaves the hardware standby st ate it performs an in ternal initialization sequence that takes 2700 extclk cycles. af ter this, it enters a low-power software standby state. while the initialization sequence is in progress, the mt9f002 will not respond to read transactions on its two-wire serial interface. therefore, a method to determine when the initialization sequence has completed is to poll a sensor register; for example, r0x0000. while the initialization sequ ence is in progress, the sensor will not respond to its device address and reads from the sensor will result in a nack on the two-wire serial interface bus. when the sequ ence has completed, reads will return the operational value for the register (0x2800 if r0x0000 is read). when the sensor leaves software standby mo de and enables the vco, an internal delay will keep the pll disconnected for up to 1ms so that the pll can lock. the vco lock time is 1ms (minimum). soft reset sequence the mt9f002 can be reset under software co ntrol by writing ?1? to software_reset (r0x0103). a software reset asynchronously re sets the sensor, truncating any frame that is in progress. the sensor starts the intern al initialization sequence, while the pll and analog blocks are turned off. at this point, the behavior is exactly the same as for the power-on reset sequence. table 9: reset_bar and pll in system states state extclks pll powered off x vco powered down por active x hardware standby 0 internal initialization 1 software standby pll lock vco powering up and locking, pll output bypassed streaming vco running, pll output active wait for frame end
mt9f002 ds rev. h pub. 6/15 en 35 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor control of the signal interface signal state during reset table 10 on page 35 shows the state of the si gnal interface during hardware standby (reset_bar asserted) and the default state du ring software standby. after exit from hardware standby and before any registers within the sensor have been changed from their default power-up values. general purpose inputs the mt9f002 provides four general purpose inputs. after reset, the input pads associ- ated with these signals are powered down by de fault, allowing the pads to be left discon- nected/floating. the general purpose inputs are enabled by setting reset_register[8] (r0x301a). once enabled, all four inputs must be driven to valid logic levels by external signals. the state of the general purpose inputs can be read through gpi_status[3:0] (r0x3026). in addition, each of the following functions ca n be associated with none, one, or more of the general purpose inputs so that the function can be directly controlled by a hardware input: ? output enable (see ?output enable control? on page 31) ? trigger/vd (slave mode) - see the sections below ? standby functions ?s addr selection (see ?serial register interface? on page 31) table 10: signal state during reset pad name pad type hardware standby software standby extclk input enabled. must be driven to a valid logic level. reset_bar (xshutdown) gpi[3:0] powered down. can be left disconnected/floating. test enabled. must be driven to a logic 0. sclk enabled. must be pulled up or driven to a valid logic level. s data i/o enabled as an input. must be pulled up or driven to a valid logic level. line_valid output high-z. can be left disconnected or floating. frame_valid d out [11:0] pixclk slvs_0p slvs_0n slvs_1p slvs_1n slvs_2p slvs_2n slvs_3p slvs_3n slvs_cp slvs_cn flash high-z. logic 0. shutter
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor control of the signal interface mt9f002 ds rev. h pub. 6/15 en 36 ?semiconductor components industries, llc,2015. the gpi_status register is used to associ ate a function with a general purpose input. streaming/standby control the mt9f002 can be switched between its so ft standby and streaming states under pin or register control, as shown in table 11. selection of a pin to use for the standby func- tion is described in ?general purpose inputs? on page 35. the state diagram for transi- tions between soft standby and streaming states is shown in figure 26 on page 33. trigger control when the global reset feature is in use, the trigger for the sequence can be initiated either under pin or register control, as show n in table 12. selection of a pin to use for the trigger function is described in ?general purpose inputs? on page 35. in slave mode, the gpi pin also serves as vd signal input. table 11: streaming/standby standby streaming r0x301aCb[2] description disabled 0 soft standby disabled 1 streaming x0 soft standby 0 1 streaming 1x soft standby table 12: trigger control trigger global trigger r0x3160C1[0] description disabled 0 idle disabled 1 trigger 00 idle x 1 trigger 1 x trigger
mt9f002 ds rev. h pub. 6/15 en 37 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor control of the signal interface clocking the sensor contains a phase-locked loop (p ll) for timing generation and control. the pll contains a prescaler to divide the input clock applied on extclk, a vco to multiply the prescaler output, and a set of dividers to generate the output clocks. the pll struc- ture is shown in figure 27 figure 27: clocking configuration f pfd = f in / (n + 1), 2 mhz ? f pfd ? 24 mhz (eq 1) f vco = f in *m/ ( n + 1), 384 mhz ? f vco ? 768 mhz (eq 2) figure 27 shows the different clocks and (in co urier font) the names of the registers that contain or are used to control their values. figure 27 also shows the default setting for each divider/multiplier control register and the range of legal values for each divider/ multiplier control register. default setup gives a physical 110 mhz internal clock for an input clock of 24 mhz. the maximum is 120 mhz. table 13: pll parameter range parameter symbol min max unit external input frequency fin 2 64 mhz pll input (pfd) frequency 2 24 mhz vco clock frequency fvco 384 768 mhz pre _ pll _clk _div (n) 2 ( 1 - 64 ) pll_ multiplier (m ) 64 ( e v e n v a l u e s : 3 2 - 3 8 4 ) ( o d d v a l u e s : 1 7 - 1 9 1 ) extclk pre pll divider pll multiplier (m) op sys clk divider clk _pixel divider e x t e r n a l i n p u t c l o c k e x t _ c l k _ f r e q _ m h z op pix clk divider op _pix _clk _div 1 2 ( 8 , 1 0 , 1 2 ) row _ speed [2 : 0 ] 1 ( 1 , 2 , 4 ) pll output clock vt sys clk divider 1 ( 1 , 2 , 4 , 6 , 8 ) vt pix clk divider clk _op divider 3 ( 2 , 3 , 4 , 5 , 6 , 7 , 8 ) row _speed [10 :8 ] 1 ( 1 , 2 , 4 ) p l l i n p u t c l o c k p l l _ i p _ c l k _ f r e q p l l i n t e r n a l v c o f r e q u e n c y v t _ p i x _ c l k _ d i v c l k _ p i x e l v t _ p i x _ c l k v t _ s y s _ c l k o p _ s y s _ c l k o p _ p i x _ c l k c l k _ o p 1 ( 1 , 2 , 4 , 6 , 8 )
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor control of the signal interface mt9f002 ds rev. h pub. 6/15 en 38 ?semiconductor components industries, llc,2015. from the diagram, the clock frequencies can be calculated as follows: note: virtual pixel clock is used as the basis for frame timing equations. (eq 3) internal pixel clock used to readout the pixel array: (eq 4) external pixel clock used to output the data: (eq 5) serial output clock: (eq 6) the parameter limit register space contains registers that declare the minimum and maximum allowable values for: ? the frequency allowable on each clock ? the divisors that are used to control each clock. the following factors determine what are vali d values, or combinations of valid values, for the divider/multiplier control registers: ? the minimum/maximum frequency limits for the associated clock must be met: ? pll_ip_clk_freq must be in the range 2- 24 mhz. lower frequencies are preferred. ?pll internal vco frequency must be in the range 384-768 mhz. ? the minimum/maximum value for the divider/multiplier must be met: range for pre_pll_clk_div: 1-64. ? clk_op must never run faster than clk_pixel to ensure that the output data stream is contiguous. ? when the serial interface is used the clk_ op divider cannot be used; row_speed[10:8] must equal 1. ? the value of op_sys_clk_div must match the bit-depth of the image when using serial interface. r0x0112-3 controls whether the pixel data interface will generate 12, 10, or 8 bits per pixel. when the pixel data interfac e is generating 8 bits per-pixel, op_pix_- clk_div must be programmed with the value 8. when the pixel data interface is gener- ating 10 bits per pixel, op_pix_clk_div must be programmed with the value 10. and when the pixel data interface is generating 12 bits per pixel, op_pix_clk_div must be programmed with the value 12. this is not required when using the parallel interface. ? although the pll vco input frequency range is advertised as 2-24 mhz, superior performance (better pll stability) is obtain ed by keeping the vco input frequency as high as possible. the usage of the output clocks is shown below: vt_pix_clk ext_clk_freq_mhz pll_multip lier 1 shift_vt_pix_clk_div + ?? ? ? pre_pll_clk_div vt_sys_clk_div ? vt_pix_clk_div ? ------------------------------------------------------------------------------------------------------------------------------- -------------------------- 24 mhz 165 2 ? ? 61 ? 6 ? ------------------------------------------- - 220 mhz === clk_pixel ext_clk_freq_mhz pll_multip lier 1 shift_vt_pix_clk_div + ?? ? ? pre_pll_clk_div vt_sys_clk_div ? vt_pix_clk_div ? 2 ? row_speed[2:0] ? ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------- 24 mhz 165 2 ? ? 61 ? 6 ? 2 ? 1 ? ------------------------------------------- - 110 mhz === clk_op ext_clk_freq_mhz pll_multiplier ? pre_pll_clk_div op_sys_clk_div ? op_pix_clk_div ? row_speed[10:8] ? ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------- - 24 mhz 165 ? 61 ? 12 ? 1 ? ---------------------------------- - 55 mhz === op_sys_clk_freq_mhz ext_clk_freq_mhz pll_multiplier ? pre_pll_clk_div op_sys_clk_div ? ---------------------------------------------------------------------------------- - 24 mhx 165 ? 61 ? ---------------------------------- - 660 mhz ===
mt9f002 ds rev. h pub. 6/15 en 39 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor control of the signal interface ? clk_pixel is used by the sensor core to control the timing of the pixel array. the sensor core produces two 10-bit pixels each clk_pixel period. the line length (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of half of the clk_pixel period. ? clk_op is used to load parallel pixel data from the output fifo. the output fifo generates one pixel each clk_op period. this clock also equals the output pixclk. ? master clock frequency corr esponds to vt_pix_clk/2. ? serial clock (op_sys_clk) used for the serial output interface. programming the pll divisors the pll divisors must be programmed while the mt9f002 is in the software standby state. after programming the divisors, wait for the vco lock time before enabling the pll. the pll is enabled by entering the streaming state. an external timer will need to delay the entr ance of the streaming mode by 1 millisecond so that the pll can lock. the effect of programming the pll divisors while the mt9f002 is in the streaming state is undefined. clock control the mt9f002 uses an aggressive clock-gating methodology to reduce power consump- tion. the clocked logic is divided into a number of separate domains, each of which is only clocked when required. when the mt9f002 enters a low-power state, almost all of the internal clocks are stopped. the only exception is that a small amount of logic is clocked so that the two- wire serial interface continues to respond to read and write requests.
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor features mt9f002 ds rev. h pub. 6/15 en 40 ?semiconductor components industries, llc,2015. features scaler the mt9f002 supports scaling capability. scaling is a ?zoom out? operation to reduce the size of the output image while covering th e same extent as the original image. that is, low resolution images can be generated wi th full field-of-view. each scaled output pixel is calculated by taking a weighted average of a group input pixels which is composed of neighboring pixels. the input and output of the scaler is in bayer format. when compared to skipping, scaling is advantageous because it uses all pixel values to calculate the output image which helps avoid aliasing. also, it is also more convenient than binning because the scale factor varies smoothly and the user is not limited to certain ratios of size reduction. the mt9f002 sensor is capable of horizontal scaling and full (horizontal and vertical) scaling. the scaling factor is programmable in 1/16 steps and is determined by. (eq 7) scale_n is fixed at 16. scale_m is adjustable with r0x0404 legal values for m are 16 through 128. the user has the ability to scale from 1:1 ( m = 16) to 1:8 ( m = 128). scaler example when horizontal and vertical scaling is en abled for a 1:2 scale factor, an image is reduced by half in both the horizontal and vertical directions. this results in an output image that is one-fourth of the orig inal image size. this can be achieved with the following register settings: r0x0400 = 0x0002 // horizontal and vertical scaling mode r0x0402 = 0x0020 // scale factor m = 32 shading correction lenses tend to produce images whose bright ness is significantly attenuated near the edges. there are also other factors causing color plane nonuniformity in images captured by image sensors. the cumulative result of all these factors is known as image shading. the mt9f002 has an embedded shading correction module that can be programmed to counter the shading effects on each individual red, greenb, greenr, and blue color signal. scalefactor = scale_n scale_m -------------------- - = 16 scale_m ------------ -------- -
mt9f002 ds rev. h pub. 6/15 en 41 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor features the correction function color-dependent solutions are calibrated using the sensor, lens system and an image of an evenly illuminated, featureless gray ca libration field. from the resulting image, register values for the color correction function (coefficients) can be derived. the correction functions can then be appl ied to each pixel value to equalize the response across the image as follows: (eq 8) where p are the pixel values and f is the color dependent correction functions for each color channel. each function includes a set of color-dependent coefficients defined by registers r0x3600?3726. the function's origin is the cent er point of the function used in the calcu- lation of the coefficients. using an origin near the central point of symmetry of the sensor response provides the best results. th e center point of the function is determined by origin_c (r0x3782) and origin_r (r0x3784) and can be used to counter an offset in the system lens from the center of the sensor array. pcorrected row, col ?? = psensor(row,col) * f(row,col)
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration mt9f002 ds rev. h pub. 6/15 en 42 ?semiconductor components industries, llc,2015. sensor readout configuration image acquisition modes the mt9f002 supports two image acquisition modes: 1. electronic rolling shutter (ers) mode this is the normal mode of operation. wh en the mt9f002 is streaming; it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. when the ers is in use, timing and control logic wi thin the sensor sequen ces through the rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate inci- dent light. the integration (exposure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset and row readout is fixed, leading to a uniform integration time across the frame. when the integration time is changed (by using the two- wire serial interface to change register settings), the timing and control logic contro ls the transition from old to new integra- tion time in such a way that the stream of output frames from the mt9f002 switches cleanly from the old integration time to the new while only generating frames with uniform integration. see ?changes to int egration time? in the mt9f002 register ref- erence. 2. global reset mode this mode can be used to acquire a single image at the current resolution. in this mode, the end point of the pixel integration ti me is controlled by an external electro- mechanical shutter, and the mt9f002 provid es control signals to interface to that shutter. the operation of this mode is described in detail in "global reset" on page 58. the benefit of using an external electromechani cal shutter is that it eliminates the visual artifacts associated with ers operation. visu al artifacts arise in ers operation, particu- larly at low frame rates, because an ers image effectively integrates each row of the pixel array at a different point in time. window control the sequencing of the pixel array is contro lled by the x_addr_start, y_addr_start, x_ad- dr_end, and y_addr_end registers. for both parallel and serial hispi interfaces, the output image size is controlled by the x_output_size and y_output_size registers. pixel border the default settings of the sensor provide a 4608h x3288v image. a border of up to 8 pixels (4 in binning) on each edge can be enabled by reprogramming the x_addr_start, y_addr_start, x_addr_end, y_addr_end, x_ou tput_size, and y_output_size registers accordingly. this provides a total active pixel array of 4640h x 3320v including border pixels.
mt9f002 ds rev. h pub. 6/15 en 43 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration readout modes horizontal mirror when the horizontal_mirror bit is set in the image_orientation register, the order of pixel readout within a row is reversed, so that re adout starts from x_addr_end and ends at x_addr_start. figure 28 shows a sequence of 6 pixels being read out with horizon- tal_mirror = 0 and horizontal_mirror = 1. changing horizontal_mirror causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register. figure 28: effect of horizontal mirror on readout order to enable image horizontal mirror mode, set register bit r0x3040[14]=1. ? 0 = normal readout ? 1 = readout is mirrored hori zontally so that the column specified by x_addr_end_ is read out of the sensor first. vertical flip when the vertical_flip bit is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. figure 29 shows a sequence of 6 rows being read out with vertical_flip = 0 and vertical_flip = 1. changing vertical_flip causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register. figure 29: effect of vertical flip on readout order to enable image vertical flip mode, set register bit r0x3040[15]=1. ? 0 = normal readout ? 1 = readout is flipped vertically so that th e row specified by y_addr_end_ is read out of the sensor first. g0[11:0] r0[11:0] g1[11:0] r1[11:0] g2[11:0] r2[11:0] r2[11:0] g2[11:0] r1[11:0] g1[11:0] r0[11:0] g0[11:0] line_valid horizontal_mirror = 0 d out [11:0] horizontal_mirror = 1 d out [11:0] row0[11:0] row1[11:0] row2[11:0] row3[11:0] row4[11:0] row5[11:0] row5[11:0] row4[11:0] row3[11:0] row2[11:0] row0[11:0] frame_valid vertical_flip = 0 d out [11:0] vertical_flip = 1 d out [11:0] row1[11:0]
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration mt9f002 ds rev. h pub. 6/15 en 44 ?semiconductor components industries, llc,2015. subsampling the mt9f002 supports subsampling. subs ampling reduces the amount of data processed by the analogue signal chain in th e sensor and thereby allows the frame rate to be increased. subsampling is enabled by changing x_odd_inc and/or y_odd_inc. values of 1, 3 and 7 can be supported for x_od d_inc, while values 1, 3, 7, 15 and 31 can be supported for y_odd_inc. setting both of these variables to 3 reduces the amount of row and column data processed and is equivalent to the skip2 readout mode provided by earlier micron imaging sensors. figure 3 shows a sequence of 8 columns being read out with x_od- d_inc=3 and y_odd_inc=1. figure 30: effect of x_odd_inc=3 on readout sequence a 1/16 reduction in resolution is achieved by setting both x_odd_inc and y_odd_inc to 7. this is equivalent to 4 x 4 skipping readout mode. figure 4 shows a sequence of 16 columns being read out with x_odd_inc=7 and y_odd_inc=1. figure 31: effect of x_odd_inc=7 on readout sequence the effect of the different subsampling settin gs on the pixel array readout is shown in figure 32through figure 38. line_valid dout g0 x_odd_inc=1 r0 g1 r1 g2 r2 g3 r3 line_valid dout g0 x_odd_inc=3 r0 g2 r2 line_valid dout g0 x_odd_inc=1 r0 g1 r1 g2 ... g7 r7 line_valid dout g0 x_odd_inc=7 r0 g4 r4
mt9f002 ds rev. h pub. 6/15 en 45 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration figure 32: pixel readout (no subsampling) figure 33: pixel readout (x_odd_inc=3, y_odd_inc=1) x incrementing y incrementing x incrementing y incrementing
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration mt9f002 ds rev. h pub. 6/15 en 46 ?semiconductor components industries, llc,2015. figure 34: pixel readout (x_odd_inc=1, y_odd_inc=3) figure 35: pixel readout (x_odd_inc=3, y_odd_inc=3) x incrementing y incrementing x incrementing y incrementing
mt9f002 ds rev. h pub. 6/15 en 47 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration figure 36: pixel readout (x_odd_inc=7, y_odd_inc=7) figure 37: pixel readout (x_odd_inc=7, y_odd_inc=15) ? x incrementing y incrementing x incrementing y incrementing
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration mt9f002 ds rev. h pub. 6/15 en 48 ?semiconductor components industries, llc,2015. figure 38: pixel readout (x_odd_inc=7, y_odd_inc=31) programming restrictions when subsampling when subsampling is enabled as a viewfinder mode and the sensor is switched back and forth between full resolution and subsamplin g, it is recommended that line_length_pck be kept constant between the two modes. this allows the same integration times to be used in each mode. x incrementing y incrementing
mt9f002 ds rev. h pub. 6/15 en 49 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration when subsampling is enabled, it may be necessary to adjust the x_addr_end, x_ad- dr_start and y_addr_end settings: the values for these registers are required to corre- spond with rows/columns that form part of the subsampling sequence. the adjustment should be made in accordance with the following rules: x_skip_factor = (x_odd_inc + 1) / 2 y_skip_factor = (y_odd_inc + 1) / 2 ? x_addr_start should be a multiple of x_skip_factor*8 ? (x_addr_end - x_addr_start + x_odd_inc) should be a multiple of x_skip_factor*8 the number of columns/rows read out with subsampling can be found from the equa- tion below: ? columns/rows = (addr_end - addr_start + odd_inc) / skip_factor summing mode summing can be enabled with binning. unlike binning mode where the values of adja- cent same color pixels are averaged together, summing adds the pixel values together, resulting in better sensor sensitivity. su mming normally provides two times the sensi- tivity compared to the binning only mode. the 2x2 summing mode can be enabled by programming the following register bit fields: r0x3178[5:4] = 3 r0x3178[7:6] = 1 to disable summing, program register bit fields above to 0. figure 39: pixel binning and summing 2x2 binning or summing v v avg summing avg avg avg avg binning avg
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration mt9f002 ds rev. h pub. 6/15 en 50 ?semiconductor components industries, llc,2015. bayer resampler the imaging artifacts found from a 2 x 2 binning will show image artifacts from aliasing. these can be corrected by resampling the sampled pixels in order to filter these artifacts. figure 40 shows the pixel location resulting from 2 x 2 binning located in the middle diagram, and the resulting pixel locations af ter the bayer resampling function has been applied. figure 40: bayer resampling the improvements from using the bayer resampling feature can be seen in figure 41. in this example, image edges seen on a diagonal have smoother edges when the bayer re- sampling feature is applied. this feature is designed to be used only with modes config- ured with 2 x 2 binning. the feature will not remove aliasing artifacts that are caused skipping pixels. figure 41: results of resampling to enable the bayer resampling feature: 1. set 0x0400 to 0x02 // enable the on-chip scalar. 2. set 0x306e to 0x90b0 // configure the on-chip scalar to resample bayer data. to disable the bayer resampling feature: 1. set 0x0400 to 0x00 // disable the on-chip scalar. 2. set 0x306e to 0x9080 // configure the on-chip scalar to resample bayer data. ? original bayer 2 x 2 binning output resampled (proper) bayer output 2 x 2 binned image bayer resampled image
mt9f002 ds rev. h pub. 6/15 en 51 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration frame rate control the formulas for calculating the frame rate of the sensor are shown below. the line length is programmed directly in pixel clock periods through register line_length_pck. for a specific window size, the minimum line length can be found from the following equation: (eq 9) note that line_length_pck also needs to m eet the minimum line length requirement set in register min_line_length_pck. the row time can either be limited by the time it takes to sample and reset the pixel array for each row, or by the time it takes to sample and read out a row. values for min_line_blanking_pck are provided in table 14 on page 52. the frame length is programmed directly in number of lines in the register frame_line_length. for a specific window si ze, the minimum frame length is shown in equation 10: (eq 10) the frame rate can be calculated from these variables and the pixel clock speed as shown in equation 11: (eq 11) if coarse_integration_time is set larger than frame_length_lines the frame size will be expanded to coarse_integration_time + 1. minimum_line_length x_addr_end x_addr_start ? 1 + subsampling factor --------------------------------------------------------------------------- min_line_blanking_pck + = minimum frame_length_lines y_addr_end - y_addr_start 1 + subsampling factor -------------------- --------------------- ------------------ ---------------- - min_frame_blanking_lines + ?? ?? = frame rate vt pixel clock mhz 1 ? 10 6 ? line_length_pck frame_length_lines ? --------------------- ------------------ ------------------ ----------------- ---------------- - =
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration mt9f002 ds rev. h pub. 6/15 en 52 ?semiconductor components industries, llc,2015. minimum row time the minimum row time and blanking values with default register settings are shown in tabl e 14 . in addition, enough time must be given to the output fifo so it can output all data at the set frequency within one row time. there are therefore three checks that must all be met when programming line_length_pck: 1. line_length_pck> min_line_length_pck 2. line_length_pck > 0.5*(x_addr_end - x_addr_start + x_odd_inc)/((1+x_odd_inc)/2) + min_line_blanking_pck 3. the row time must allow the fifo to output all data during each row. that is, ? for parallel interface: line_length_pck > (x_output_size) * ?vt_pix_clk period? / ?op_pix_clk period? + 0x005e ?for hispi (4-lane): line_length_pck > (1/4)*(x_output_size) * ?vt_pix_cl k period? / ?op_pix_clk period? + 0x005e minimum frame time the minimum number of rows in the image is 2, so min_frame_length_lines will always equal (min_frame_blanking_lines + 2). table 14: minimum row time and blanking numbers register no row binning row binning row_speed[2:0] 1 2 4 1 2 4 min_line_blanking_pck 0x0138 0x0138 0x0138 0x00e8 0x00e8 0x00e8 min_line_length_pck 0x04c8 0x0278 0x0278 0x0968 0x04b8 0x0260 table 15: minimum frame time and blanking numbers register min_frame_blanking_lines 0x0092 min_frame_length_lines 0x0094
mt9f002 ds rev. h pub. 6/15 en 53 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor readout configuration integration time the integration (exposure) time of the mt9f 002 is controlled by the fine_integration_- time and coarse_integration_time registers. the limits for the fine inte gration time are defined by: fine_integration_time_min < fine_integration_time < (line_length_pck ? (eq 12) fine_integration_time_max_margin the limits for the coarse integration time are defined by: coarse_integration_time_min < coarse_integration_time (eq 13) the actual integratio n time is given by: (eq 14) it is required that: coarse_integration_time < = (frame_length_lines - coarse_integration_time_max_margin) (eq 15) if this limit is exceeded, the frame time will automatically be extended to ( coarse_inte- gration_time + coarse_integartion_time_max_margin ) to accommodate the larger inte- gration time. fine integration time limits the limits for the fine_integration_time ca n be found from fine _integration_ time_min and fine_integration_time_max_margin. it is necessary to change fine_correction (r0x3010) when binning is enabled or the pixel clock divider (row_speed[2:0]) is used. the corresponding fine_correction values are shown in table 16. fine correction for the fine_integration_time limits, the fine _correction constant will change with the pixel clock speed and binning mode. table 16: fine_integration_time limits register no row binning row binning row_speed[2:0] 1 2 4 1 2 4 fine_integration_time_min 0x02b0 0x0158 0x0ac 0x05f2 0x02fa 0x017e fine_integration_time_max_margin 0x0212 0x0109 0x0086 0x0376 0x01ba 0x00dc table 17: fine_correction values register no row binning row binning row_speed[2:0] 1 2 4 1 2 4 fine_correction 0x094 0x044 0x01c 0x0183 0x0bb 0x057 integration_time coarse_integration_time * line_length_pck ?? fine_integration_time + ?? vt_pix_clk_freq_mhz*10 6 ?? ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------- =
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts mt9f002 ds rev. h pub. 6/15 en 54 ?semiconductor components industries, llc,2015. power mode contexts the mt9f002 sensor supports power consumption optimization through the power mode contexts. depending on the sensor operating mode, th e appropriate power context can be programmed through register r0x30e8 as shown in table 18 below. programming register r0x30e8 will internally set the analog bias current reserved regis- ters to predetermined values which result in optimized bias currents in the analog domain. register r0x30e8 is not ?frame sync'd,? and should be programmed when frame_valid is not active, in order to avoid a ?bad frame.? table 18: power mode contexts power mode context register address recommended value description 1 r0x30e8 0x8001 reserved 2 r0x30e8 0x8002 reserved 3 r0x30e8 0x8003 reserved 4 rr0x30e8 0x8004 reserved 5 r0x30e8 0x8005 reserved 6 r0x30e8 0x8006 reserved 7 r0x30e8 0x8007 reserved
mt9f002 ds rev. h pub. 6/15 en 55 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts on semiconductor gain model the on semiconductor gain model uses color-specific registers to control both analog and digital gain to the sensor. these registers are: ? global_gain ?greenr_gain ?red_gain ? blue_gain ?greenb_gain the registers provide three analog gain stag es. the analog_gain_2 analog gain stage has a granularity of 64 steps over 2x gain. a digital gain (gain<15:12>) from 1-15x can also be applied. analog gain = 2^gain<11:10> x 2^ gain<9:7> x gain<6:0>/64 (eq 16) digital_gain = gain<15:12> (eq 17) total gain = digital_gain x analog_gain (eq 18) analog gain stages the analog gain stages of the mt9f002 sensor are shown in figure 1. the recommended gain settings enable gain increases very early in the signal chain (such as in the colamp), so the signal can be effectively boosted while amplifying as few noise sources as possible. figure 42: analog gain stages as a result of the different gain stages, anal og gain levels can be achieved in different ways. the recommended gain settings are shown in table 19 on page 56. colamp_gain asc1 analog_gain_2 (asc2_fine_gain) analog_gain_3 1x, 2x, 4x and 8x 1x 1x to 1.984375x 1x, 2x gain = 2^gain[11:10] gain= gain [6:0]/64 gain = 2^gain[9:7] pixel offset can cellation digital_gain gain = gain[15:12]
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts mt9f002 ds rev. h pub. 6/15 en 56 ?semiconductor components industries, llc,2015. note: these gain settings reflects maximizing the front-end colamp_gain, while meeting the minimum requirement of 0.75 for the analog_gain_2 stage. in order to ensure adc saturation, the recommended minimum gain (minimum iso speed equivalent gain) setting for the mt9f002 sensor (rev3) is 1.50. also, the recommended maximum analog gain is 15.875. for total gain values greater than 15.875, use or increase digital gain. flash control the mt9f002 supports both xenon and led flash through the flash output signal. the timing of the flash signal with the defa ult settings is shown in figure 43, and in figure 44 and figure 45 on page 57. the flash and flash_count registers allow the timing of the flash to be changed. the flash can be programmed to fire only once, delayed by a few frames when asserted, and (for xenon fl ash) the flash duration can be programmed. enabling the led flash will cause one bad frame, where several of the rows only have the flash on for part of their integration time. th is can be avoided either by first enabling mask bad frames (write reset_register[9] = 1) before the enabling the flash or by forcing a restart (write reset_register[1] = 1) immediat ely after enabling the flash; the first bad frame will then be masked out, as shown in figure 45 on page 57. read-only bit flash[14] is set during frames that are correctly int egrated; the state of this bit is shown in figures 43, 44, and 45. figure 43: xenon flash enabled table 19: recommended register settings gain range register setting colamp_gain analog_gain 3 analog_gain_2 digital gain 1.50 - 2.969 0x1430 - 0x145f 2x 1x 0.75 - 1.484 1x 3.00 - 5.938 0x1830 - 0x185f 4x 1x 0.75 - 1.484 1x 6.00 - 15.875 0x1c30 - 0x1c7f 8x 1x 0.75 - 1.984 1x 16.00 - 31.75 0x2c40 - 0x2c7f 8x 1x 1.00 - 1.984 2x 32.00 - 63.50 0x4c40 - 0x4c7f 8x 1x 1.00 - 1.984 4x frame_valid flash strobe state of triggered bit (r0x3046-7[14])
mt9f002 ds rev. h pub. 6/15 en 57 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts figure 44: led flash enabled notes: 1. integration time = number of rows in a frame. 2. bad frames will be masked during led flash operation when mask bad frames bit field is set (r0x301a[9] = 1). 3. an option to invert the flash output si gnal through r0x3046[7] is also available. figure 45: led flash enabled following forced restart bad frame frame_valid flash strobe state of triggered bit (r0x3046-7[14]) flash enabled bad frame good frame good frame flash disabled during this frame during this f rame flash enabled masked out good frame good frame flash disabled and a restart frame and a restart triggered triggered frame_valid flash strobe state of triggered bit (r0x3046-7[14]) masked out frame
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts mt9f002 ds rev. h pub. 6/15 en 58 ?semiconductor components industries, llc,2015. global reset global reset mode allows the integration time of the mt9f002 to be controlled by an external electromechanical shutter. global reset mode is generally used in conjunction with ers mode. the ers mode is used to prov ide viewfinder informat ion, the sensor is switched into global reset mode to captur e a single frame, and the sensor is then returned to ers mode to restore viewfinder operation. overview of global reset sequence the basic elements of the global reset sequence are: 1. by default, the sensor operates in ers mo de and the shutter output signal is low. the electromechanical shutter must be open to allow light to fall on the pixel array. integration time is controlled by the co arse_integration_time and fine_integration_- time registers. 2. a global reset sequence is triggered. 3. all of the rows of the pixel array are placed in reset. 4. all of the rows of the pixel array are taken out of reset simultaneously. all rows start to integrate incident light. the electromechanical shutter may be open or closed at this time. 5. if the electromechanical shutter has been closed, it is opened. 6. after the desired integration time (controlle d internally or externally to the mt9f002), the electromechanical shutter is closed. 7. a single output frame is generated by th e sensor with the usual lv, fv, pixclk, and d out timing. as soon as the output frame ha s completed (fv de-asserts), the electro- mechanical shutter ma y be opened again. 8. the sensor automatically resumes operation in ers mode. this sequence is shown in figure 46. the fo llowing sections expand to show how the timing of this sequ ence is controlled. figure 46: overview of global reset sequence entering and leaving the global reset sequence a global reset sequence can be triggered by a register write to global_seq_trigger[0] (global trigger, to transition this bit from a 0 to a 1) or by a rising edge on a suit- ably-configured gpi input (see ?trigger control? on page 36). when a global reset sequence is triggered, the sensor waits for the end of the current row. when lv de-asserts for that row, fv is de-asserted 6 pixclk periods later, potentially truncating the frame that was in progress. the global reset sequence completes with a frame readout. at the end of this readout phase, the sensor automatically resumes op eration in ers mode. the first frame inte- grated with ers will be generated after a delay of approximately: ((13 + coarse_integration_time) * line_length_pck). this sequence is shown in figure 47. ers ers row reset integration readout
mt9f002 ds rev. h pub. 6/15 en 59 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts while operating in ers mode, double-buffered registers are updated at the start of each frame in the usual way. during the global reset sequence, double-buffered registers are updated just before the start of the readout phase. figure 47: entering and leaving a global reset sequence programmable settings the registers global_rst_end and global_read_ start allow the duration of the row reset phase and the integration phase to be controll ed, as shown in figure 48. the duration of the readout phase is determined by the active image size. as soon as the global_rst_end count has expired, all rows in the pixel array are simulta- neously taken out of reset and the pixel array begins to integrate incident light. figure 48: controlling the reset and integr ation phases of the global reset sequence ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end global_read_start
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts mt9f002 ds rev. h pub. 6/15 en 60 ?semiconductor components industries, llc,2015. control of the electromechanical shutter figure 49 shows two different ways in which a shutter can be controlled during the global reset sequence. in both cases, the ma ximum integration time is set by the differ- ence between global_read_start and global_rst_end. in shutter example 1, the shutter is open during the initial ers sequence and duri ng the row reset phase. the shutter closes during the integration phase. the pixel array is integrating incident light from the start of the integration phase to the point at wh ich the shutter closes. finally, the shutter opens again after the end of the readout phase. in shutter example 2, the shutter is open during the initial ers sequence and closes sometime during the row reset phase. the shutter both opens and closes during the int egration phase. the pixel array is integrating incident light for the part of the integration phase during which the shutter is open. as for the previous example, the shutter opens again after the end of the readout phase. figure 49: control of the electromechanical shutter it is essential that the shutter remains clos ed during the entire row readout phase (that is, until fv has de-asserted for the frame readou t); otherwise, some rows of data will be corrupted (over-integrated). it is essential that the shutte r closes before the end of the integration phase. if the row readout phase is allowed to start before the shutter closes, each row in turn will be inte- grated for one row-time longer than the previous row. after fv de-asserts to signal the completion of the readout phase, there is a time delay of approximately 10 * line_length_pck before the sensor starts to integrate light-sensitive rows for the next ers frame. it is essential that the shutter be opened at some point in this time window; otherwise, the first er s frame will not be uniformly integrated. the mt9f002 provides a shutter output sign al to control (or help the host system control) the electromechanical shutter. the timing of the shutter output is shown in figure 50 on page 61. shutter is de-asserted by default. the point at which it asserts is controlled by the programming of global_shu tter_start. at the end of the global reset readout phase, shutter de-asserts approximately 2 * line_length_pck after the de- assertion of fv. this programming restriction must be met for correct operation: global_read_start > global_shutter_start ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end global_read_start maximum integration time shutter open shutter open shutter closed actual integration time shutter open shutter open shutter closed closed shutter open actual integration time shutter example 1 shutter example 2
mt9f002 ds rev. h pub. 6/15 en 61 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts figure 50: controlling the shutter output using flash with global reset if global_seq_trigger[2] = 1 (global flash enabled) when a global reset sequence is trig- gered, the flash output signal will be pulsed during the integration phase of the global reset sequence. the flash output will assert a fixed number of cycles after the start of the integration phase and will remain asserted for a time that is controlled by the value of the flash_count register, as shown in figure 51. figure 51: using flash with global reset external control of integration time if global_seq_trigger[1] = 1 (global bulb enabled) when a global reset sequence is trig- gered, the end of the integration phase is co ntrolled by the level of trigger (global_se- q_trigger[0] or the associated gpi input). this allows the integration time to be controlled directly by an input to the sensor. this operation corresponds to the shutter ?b ? setting on a traditional camera, where ?b? originally stood for ?bulb? (the shutter setting used for synchronization with a magne- sium foil flash bulb) and was later considered to stand for ?brief? (an exposure that was longer than the shutter coul d automatically accommodate). when the trigger is de-asserted to end integrat ion, the integration phase is extended by a further time given by global_read_start ? global_shutter_start . usually this means that global_read_start should be set to global_shutter_start + 1 . the operation of this mode is shown in figure 52 on page 62. the figure shows the global reset sequence being triggered by the gpi2 input, but it could be triggered by any of the gpi inputs or by the setting and subsequence clearing of the global_seq_trigger[0] under software control. ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end global_read_start shutter global_shutter_start ~2*line_length_pck ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end flash flash_count (fixed)
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts mt9f002 ds rev. h pub. 6/15 en 62 ?semiconductor components industries, llc,2015. the integration time of the grr sequence is defined as: (eq 19) where: (eq 20) (eq 21) the integration equation allo ws for 24-bit precision when calculating both the shutter and readout of the image. the global_rst_end has only 16-bit as th e array reset function and requires a short amount of time. the integration time can also be scaled using global_scale. the variable can be set to 0?512, 1?2048, 2?128, and 3?32. these programming restrictions must be me t for correct operation of bulb exposures: ? global_read_start > global_shutter_start ? global_shutter_start > global_rst_end ? global_shutter_start must be smaller than the exposure time (that is, this counter must expire before the trigger is de-asserted) figure 52: global reset bulb retriggering the global reset sequence the trigger for the global reset sequence is edge-sensitive; the gl obal reset sequence cannot be retriggered until the global trigger bit (in the global_seq_trigger register) has been returned to ?0,? and the gpi (if any) as sociated with the trigger function has been de-asserted. the earliest time that the glob al reset sequence can be retriggered is the point at which the shutter output de-asserts; this occurs approximately 2 * line_length_pck after the negation of fv for the global reset readout phase. the frame that is read out of the sensor duri ng the global reset readout phase has exactly the same format as any other frame out of th e serial pixel data interface, including the addition of two lines of embedded data. the values of the coarse_integration_time and fine_integration_time registers within the embedded data match the programmed values of those registers and do not reflect the integration time used during the global reset sequence. integration time global _ scale [ global _ read _ start global _ shutter _ start ? global _ rst _ end ] ? ? vt _ pix _ clk _ freq _ mhz ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------- - = global _ read _ start 2 16 global _ read _ start 27:0 ?? ? global _ read _ start 115:0 ?? + ?? = global _ shutter _ start 2 16 global _ shutter _ start 27:0 ?? ? global _ shutter _ start 115:0 ?? + ?? = ers ers row reset integration readout trigger wait for end of current row automatic at end of frame readout global_rst_end gpi2 global_read_start - global_shutter_start
mt9f002 ds rev. h pub. 6/15 en 63 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts global reset and soft standby if the mode_select[stream] bit is cleared while a global reset sequence is in progress, the mt9f002 will remain in streaming state until the global reset sequence (including frame readout) has completed, as shown in figure 53. figure 53: entering soft standb y during a global reset sequence slave mode the mt9f002 sensor supports slave mode to sync the frame rate more precisely, and simply by the vd signal from external asic. the vd signal also allows for precise control of frame rate and register change updates. the vd signal for slave grr mode is synchronized to ers frame time, so that sensor can complete the current frame readout in ers mode before moving to grr mode, and avoid ers broken frame before moving into grr mode. control bit vd_trigger_new_- frame bit allows vd triggering every new frame. a gpi pin on the sensor can be programmed to act as vd input pin signal whose rising edge can be used to start every new frame (see figure 55 for details). an optional functionality to limit the durati on counters are halted is given by setting vd_timer bit to 1. when this bit is set the coun ters will not wait indefinitely for vd rising edge & resume normal counting after halting for a limited time. otherwise when vd_timer is set to 0, internal row and column counters are halted until the arrival of vd's positive edge. slave mode grr global reset sequence is triggered by progra mming the global_seq_trigger bit. after this register bit is written the sensor will wait fo r rising edge of vd signal at the end of the current frame to go into grr mode. the control bit needed to be set to enable this func- tionality is vd_trigger_grst. on ce in the grr integration phase, the sensor will wait for the next vd rising edge to begin the readout. at the end of the readout phase, the sensor automatically resumes operation in ers mode with readout of successive frames starting with rising edge of vd. figure 54: ?slave mode grr timing,? on page 64 and figure 55: ?slave mode hispi output (ers to grr transition),? on page 64 are related timing diagrams: ers ers row reset integration readout mode_select[streaming] system state software standby streaming
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor power mode contexts mt9f002 ds rev. h pub. 6/15 en 64 ?semiconductor components industries, llc,2015. slave mode grr timing for example, to switch between ers and grr (and back to ers), see figure 54: figure 54: slave mode grr timing figure 55: slave mode hispi output (ers to grr transition) when grr is triggered (by the rising edge of vd signal), the mt9f002 sensor starts grr sequence and also send a start-of-blanking (sob) sync code at the end of current ers frame. it continues to send sob sync codes during the entire grr sequence. sensor internal frame-valid signal sensor internal line-valid signal grr integration grr frame readout global reset sequence internal sensor ?start of frame? & register sync point vertical blanking (144 rows likely) change in row-time using group_parame ter_hold is implemented at the internal ?sof? ?start of active? sync code ?start of blanking? sync code active image data transmitted on hispi blanking words transmitted on hispi grr trigger (global_read_start ? global_shutter_start) vd internal sensor ?start of frame? & register sync point
mt9f002 ds rev. h pub. 6/15 en 65 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor core digital data path sensor core digital data path test patterns the mt9f002 supports a number of test pa tterns to facilitate system debug. test patterns are enabled using test_pattern_mode (r0x0600?1). the test patterns are listed in table 20. test patterns 0?3 replace pixel data in the output image (the embedded data rows are still present). test pattern 4 replaces all data in the output image (the embedded data rows are omitted and test pattern data replaces the pixel data). hispi test patterns test patterns specific to the hispi are also generated. the test patterns are enabled by using test_enable (r0x31c6 - 7) and controlled by test_mode (r0x31c6[6:4]). for all of the test patterns, the mt9f002 registers must be set appropriately to control the frame rate and output timing. this includes: ?all clock divisors ? x_addr_start ? x_addr_end ? y_addr_start ? y_addr_end ? frame_length_lines ?line_length_pck ?x_output_size ? y_output_size table 20: test patterns test_pattern_mode description 0 normal operation: no test pattern 1 solid color 2 100% color bars 3fade-to-gray color bars 4 pn9 link integrity pattern (only on sensors with serial interface) 256 walking 1s (12-bit value) 257 walking 1s (10-bit value) 258 walking 1s (8-bit value) table 21: hispi test patterns test_mode description 0 transmit a constant 0 on all enabled data lanes. 1 transmit a constant 1 on all enabled data lanes. 2 transmit a square wave at half the serial data rate on all enabled data lanes. 3 transmit a square wave at the pixel rate on all enabled data lanes. 4 transmit a continuous sequence of pseudo random da ta, with no sav code, copied on all enabled data lanes. 5 replace data from the sensor with a known sequence copied on all enabled data lanes.
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor core digital data path mt9f002 ds rev. h pub. 6/15 en 66 ?semiconductor components industries, llc,2015. effect of data path processing on test patterns test patterns are introduced early in the pixel data path. as a result, they can be affected by pixel processing that occurs wi thin the data path. this includes: ? noise cancellation ? black pedestal adjustment ? lens and color shading correction these effects can be eliminated by the following register settings: ? r0x3044-5[10] = 0 ? r0x30ca-b[0] = 1 ? r0x30d4-5[15] = 0 ? r0x31e0-1[0] = 0 ? r0x3180-1[15] = 0 ? r0x301a-b[3] = 0 (enable writes to data pedestal) ? r0x301e-f = 0x0000 (set data pedestal to 0) ? r0x3780[15] = 0 (turn off lens/color shading correction) solid color test pattern in this mode, all pixel data is replaced by fixed bayer pattern test data. the intensity of each pixel is set by its associated test data register (test_data_red, test_data_greenr, test_data_blue, test_data_greenb). 100% color bars test pattern in this test pattern, shown in figure 41 on page 127, all pixel data is replaced by a bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, black). each bar is 1/8 of the width of the pi xel array. the pattern repeats after eight bars. each color component of each bar is set to either 0 (fully off) or 0x3f f (fully on for 10-bit data). the pattern occupies the full height of the output image. the image size is set by x_addr_start, x_ad dr_end, y_addr_start, y_addr_end and may be affected by the setting of x_output_size, y_ output_size. the color-bar pattern is discon- nected from the addressing of the pixel array, and will therefore always start on the first visible pixel, regardless of the value of x_addr_start. the number of colors that are visible in the output is dependent upon x_addr_end - x_addr_start and the setting of x_out- put_size: the width of each color bar is fixed. the effect of setting horizontal_mirror in conjunction with this test pattern is that the order in which the colors are generated is reversed: the black bar appears at the left side of the output image. any pattern repeat occu rs at the right side of the output image regardless of the setting of horizontal_mirror. the state of vertical_flip has no effect on this test pattern. the effect of subsampling, binning, and scaling of this test pattern is undefined.
mt9f002 ds rev. h pub. 6/15 en 67 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor core digital data path figure 56: 100% color bars test pattern fade-to-gray color bars test pattern in this test pattern, shown in figure 42 on page 128, all pixel data is replaced by a bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, black). each bar is 1/8 of the width of the pixel array (2592/8 = 324 pixels). the test pattern repeats after 2592 pixels. each color ba r fades vertically from zero or full inten- sity at the top of the image to 50 percent inte nsity (mid-gray) on the last (968th) row of the pattern. each color bar is divided into a left and a right half, in which the left half fades smoothly and the right half fades in quantized steps. the speed at which each color fades is dependent on the sensor's data width and the he ight of the pixel array. we want half of the data range (from 100 or 0 to 50 percent) difference between the top and bottom of the pattern. because of the bayer pattern, each state must be held for two rows. the rate-of-fade of the bayer pattern is set so that there is at least one full pattern within a full-sized image for the sensor. factors that affect this are the resolution of the adc (10-bit or 12-bit) and the image height. for example, the mt9p013 fades the pixels by 2 lsb for each two rows. with 12-bit data, the pattern is 2048 pixels high and repeats after that, if the window is higher. the image size is set by x_addr_start, x_ad dr_end, y_addr_start, y_addr_end and may be affected by the setting of x_output_size, y_ output_size. the color-bar pattern starts at the first column in the image, regardless of the value of x_addr_start. the number of colors that are visible in the output is de pendent upon x_addr_end - x_addr_start and the setting of x_output_size: the width of each color bar is fixed at 324 pixels. the effect of setting horizontal_mirror or vertical_flip in conjunction with this test pattern is that the order in which the colors are generated is reversed: the black bar appears at the left side of the output image. any pattern repeat occurs at the right side of the output image regardless of the setting of horizontal_mirror. the effect of subsampling, binning, and scaling of this test pattern is undefined. horizontal mirror = 0 horizontal mirror = 1
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor core digital data path mt9f002 ds rev. h pub. 6/15 en 68 ?semiconductor components industries, llc,2015. figure 57: fade-to-gray color bar test pattern pn9 link integrity pattern the pn9 link integrity pattern is intended to al low testing of a serial pixel data interface. unlike the other test patterns, th e position of this test pattern at the end of the data path means that it is not affected by other data path corrections (row noise, pixel defect correction and so on). this test pattern provides a 512-bit pseudo-ran dom test sequence to test the integrity of the serial pixel data output stream. the polyno mial x9 + x5 + 1 is used. the polynomial is initialized to 0x1ff at the start of each frame. when this test pattern is enabled: ? the embedded data rows are disabled an d the value of frame_format_decriptor_1 changes from 0x1002 to 0x1000 to indicate that no rows of embedded data are present. ? the whole output frame, bounded by th e limits programmed in x_output_size and y_output_size, is fill ed with data from the pn9 sequence. ? the output data format is (effectively) fo rced into raw10 mode regardless of the state of the ccp_data_format register. before enabling this test pattern the clock divisors must be configured for raw10 opera- tion (op_pix_clk_div = 10). this polynomial generates this sequence of 10-bit values: 0x1ff, 0x378, 0x1a1, 0x336, 0x385... on the parallel pixel data output, th ese values are presented 10-bits per pixclk. on the serial pixel data output, these values are streamed out sequentially without performing the raw10 packing to bytes that normally occurs on this interface. horizontal mirror = 0, vertical flip = 0 horizontal mirro r = 1, vertical flip = 0 horizontal mirror = 0, vertical flip = 1 horizontal mirro r = 1, vertical flip = 1
mt9f002 ds rev. h pub. 6/15 en 69 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor core digital data path walking 1s when selected, a walking 1s pattern will be sent through the digital pipeline. the first value in each row is 0. each value will be valid for two pixels. figure 58: walking 1s 12-bit pattern figure 59: walking 1s 10-bit pattern figure 60: walking 1s 8-bit pattern the walking 1s pattern was implemented to faci litate assembly testing of modules with a parallel interface. the walking 1 test pattern is not active during the blanking periods; hence the output would reset to a value of 0x0. when the active period starts again, the pattern would restart from the beginning. the be havior of this test pattern is the same between full resolution and subsampling mode. raw10 and raw8 walking 1 modes are enabled by different test pattern codes. test cursors the mt9f002 supports one horizontal and one ve rtical cursor, allowing a crosshair to be superimposed on the image or on test pa tterns 1?3. the position and width of each cursor are programmable in r0x31e8?r0x31ee. both even and odd cursor positions and widths are supported. each cursor can be inhibited by setting its width to ?0.? the programmed cursor position corresponds to the x and y addresses of the pixel array. for example, setting horizon- tal_cursor_position to the same value as y_add r_start would result in a horizontal cursor line_valid dout (hex) 000 pixclk 000 001 001 002 002 004 004 008 008 010 010 020 020 040 040 800 800 fff fff 000 080 080 100 100 200 200 400 400 line_valid dout (hex) 000 pixclk 000 001 001 002 002 004 004 008 008 010 010 020 020 040 040 000 000 001 001 002 080 080 100 100 200 200 fff fff line_valid dout (hex) 00 pixclk 00 01 01 02 02 04 04 08 08 10 10 20 20 40 40 02 02 04 04 08 80 80 ff ff 00 00 01 01
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor sensor core digital data path mt9f002 ds rev. h pub. 6/15 en 70 ?semiconductor components industries, llc,2015. being drawn starting on the first row of the image. the cursors are opaque (they replace data from the imaged scene or test pattern). th e color of each cursor is set by the values of the bayer components in the test_data_ red, test_data_greenr, test_data_blue and test_data_greenb registers. as a consequence, the cursors are the same color as test pattern 1 and are therefore invisible when test pattern 1 is selected. when vertical_cursor_position = 0x0fff, the vertical cursor operates in an automatic mode in which its position advances every fram e. in this mode the cursor starts at the column associated with x_addr_start = 0 and advances by a step-size of 8 columns each frame, until it reaches the column associat ed with x_addr_start = 2040, after which it wraps (256 steps). the width and color of the cursor in this automatic mode are controlled in the usual way. the effect of enabling the test cursors when the image_orientation register is non-zero is not defined by the design specification. the behavior of the mt9f002 is shown in figure 61 on page 70 and the test cursors are shown as translucent, for clarity. in prac- tice, they are opaque (they overlay the im aged scene). the manner in which the test cursors are affected by the value of image_ orientation can be understood from these implementation details: ? the test cursors are inserted last in the da ta path, the cursor is applied with out any sensor corrections. ? the drawing of a cursor starts when the pi xel array row or column address is within the address range of cursor start to cursor start + width. ? the cursor is independent of image orientation. figure 61: test cursor behavior with image orientation readout direction vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 1 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 1 readout direction readout direction readout direction
mt9f002 ds rev. h pub. 6/15 en 71 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor timing specifications timing specifications power-up sequence the recommended power-up sequence for the mt9f002 is shown in figure 62. the available power supplies?v dd _io, v dd , v dd _pll, v aa , v aa _pix, v dd _hisp i , v dd _tx can be turned on at the same time or have the separation specified below. 1. turn on v dd _io power supply. 2. after 1?500ms, turn on v dd and v dd _ hispi power supplies. 3. after 1?500ms, turn on v dd _pll and v aa /v aa _pix power supplies. 4. after 1?500ms, turn on v dd _tx power supply 5. after the last power supply is stable, enable extclk. 6. assert reset_bar for at least 1ms. 7. wait 2700 extclks for internal initialization into software standby. 8. configure pll, output, and image settings to desired values 9. set mode_select = 1 (r0x0100). 10. wait 1ms for the pll to lock before streaming state is reached. figure 62: power-up sequence note: digital supplies must be turned on before analog supplies. table 22: power-up sequence definition symbol min typ max unit v dd _io to v dd , v dd _hispi time t 10C500ms v dd , v dd _hispi to v dd _pll time t 20C500ms v dd _pll to v aa /v aa _pix time t 30C500ms v aa , v aa _pix to v dd _tx t 4CC500ms active hard reset t 5 1CC ms internal initialization t 6 2700 C C extclks pll lock time t 7 1CC ms internal init hard reset software standby pll lock streaming t 1 t 2 t 3 t 5 t 6 t 7 v dd_ tx t 4 v aa , v aa _pix extclk v dd _pll v dd, v dd_ hispi v dd_ io reset_bar
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor timing specifications mt9f002 ds rev. h pub. 6/15 en 72 ?semiconductor components industries, llc,2015. power-down sequence the recommended power-down sequence for the mt9f002 is shown in figure 63. the available power supplies?v dd _io, v dd , v dd _pll, v aa , v aa _pix, v dd _hispi, and v dd _tx?can be turned off at the same time or have the separation specified below. 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. assert hard reset by setti ng reset_bar to a logic ?0.? 4. turn off the v dd _tx, v aa /v aa _pix, and v dd _pll power supplies. 5. after 1 ? 500ms, turn off v dd and v dd _hispi power supply. 6. after 1 ? 500ms, turn off v dd _io power supply. figure 63: power-down sequence table 23: power-down sequence definition symbol min typ max unit hard reset t 1 1CC ms v dd _tx to v dd time t 20C500ms v dd /v aa /v aa _pix to v dd time t 30C500ms v dd _pll to v dd time t 40C500ms v dd to v dd _io time t 50C500ms t 5 t 4 t 3 v dd _ io v dd , v dd _h i sp i v dd _pll v aa , vaa_pix v dd _tx extclk reset_bar turning off power supplies hard reset software standby streaming t 1 t 2
mt9f002 ds rev. h pub. 6/15 en 73 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor timing specifications hard standby and hard reset the hard standby state is reached by the as sertion of the reset_bar pad (hard reset). register values are not retained by this action, and will be returned to their default values once hard reset is completed. the minimum power consumption is achieved by the hard standby state. the details of the sequence are described below and shown in figure 64 on page 73. 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. assert reset_bar (active low) to reset the sensor. 4. the sensor remains in hard standby state if reset_bar remains in the logic ?0? state. figure 64: hard standby and hard reset extclk mode_select r0x0100 reset_bar logic 1 logic 0 streaming soft standby hard standby from hard reset next row/frame
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor timing specifications mt9f002 ds rev. h pub. 6/15 en 74 ?semiconductor components industries, llc,2015. soft standby and soft reset the mt9f002 can reduce power consumption by switching to the soft standby state when the output is not needed. register valu es are retained in the soft standby state. once this state is reached, soft reset can be enabled optionally to return all register values back to the default. the details of the sequence are described below and shown in figure 65. soft standby 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. soft reset 1. follow the soft standby sequence listed above. 2. set software_reset = 1 (r0x0103) to start the internal initialization sequence. 3. after 2700 extclks, the internal initializa tion sequence is completed and the current state returns to soft standby automatically. all registers, including software_reset, return to their default values. figure 65: soft standby and soft reset extclk mode_select r0x0100 software_reset r0x0103 logic 1 logic 0 streaming soft s tandby soft reset soft standby next row/frame logic 0 logic 1 logic 0 2700 extclks logic 0 logic 0 logic 0
mt9f002 ds rev. h pub. 6/15 en 75 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor spectral characteristics spectral characteristics figure 66: quantum efficiency 0 10 20 30 40 50 60 350 400 450 500 550 600 650 700 750 quantum efficiency (%) wavelength (nm) r g b
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor spectral characteristics mt9f002 ds rev. h pub. 6/15 en 76 ?semiconductor components industries, llc,2015. table 24: 11.4 chief ray angle image height cra (%) (mm) (deg) 000 5 0.192 0.57 10 0.384 1.14 15 0.575 1.71 20 0.767 2.28 25 0.959 2.85 30 1.151 3.42 35 1.343 3.99 40 1.534 4.56 45 1.726 5.13 50 1.918 5.70 55 2.110 6.27 60 2.302 6.84 65 2.493 7.41 70 2.685 7.98 75 2.877 8.55 80 3.069 9.14 85 3.261 9.69 90 3.452 10.26 95 3.644 10.83 100 3.836 11.40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 102030405060708090100110 cra (deg) image height (%)
mt9f002 ds rev. h pub. 6/15 en 77 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor spectral characteristics reading the sensor cra follow the steps below to obtain the cra value of the image sensor: 1. set the register bit field r0x301a[5] = 1. 2. read the register bit fields r0x31fa[11:9]. 3. determine the cra value according to table 26. table 25: 25 chief ray angle image height cra (%) (mm) (deg) 00 0 5 0.192 2.16 10 0.384 4.27 15 0.575 6.35 20 0.767 8.41 25 0.959 10.45 30 1.151 12.44 35 1.343 14.37 40 1.534 16.21 45 1.726 17.93 50 1.918 19.49 55 2.110 20.89 60 2.302 22.10 65 2.493 23.10 70 2.685 23.88 75 2.877 24.46 80 3.069 24.83 85 3.261 25.00 90 3.452 25.00 95 3.644 24.84 100 3.836 24.56 table 26: cra value binary value of r0x31fa[11:9] cra value 000 0 001 25 010 11.4 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 102030405060708090100 cra (deg) image height (%)
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics mt9f002 ds rev. h pub. 6/15 en 78 ?semiconductor components industries, llc,2015. electrical characteristics caution stresses greater than those listed in table 28 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. notes: 1. exposure to absolute maximum rating cond itions for extended periods may affect reliability. table 27: dc electrical defi nitions and characteristics f extclk = 24 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _hispi = 1.8v, v dd _tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 660 mbps; dll set to 0, 14mp frame-rate at 13.65 fps definition condition symbol min typ max unit core digital voltage v dd 1.7 1.8 1.9 v i/o digital voltage v dd _io 1.7 1.8 1.9 v analog voltage v aa 2.7 2.8 3.1 v pixel supply voltage v aa _pix 2.7 2.8 3.1 v pll supply voltage v dd _pll 2.4 2.8 3.1 v hispi digital voltage v dd _hispi 1.7 1.8 1.9 v hispi i/o digital voltage slvs hivcm v dd _tx 0.3 1.7 0.4 1.8 0.9 1.9 v v digital operating current serial hispi slvs @ 13.65fps 75.0 ma i/o digital operating current serial hispi slvs @ 13.65fps 1.2 ma analog operating current serial hispi slvs @ 13.65fps 172 ma pixel supply current serial hispi slvs @ 13.65fps 5.6 ma pll supply current serial hispi slvs @ 13.65fps 12.3 ma hispi digital operating current s erial hispi slvs @ 13.65fps 28.6 ma hispi i/o digital operating current serial hispi slvs @ 13.65fps 10.5 ma digital operating current parallel interface @ 6.3fps 65.0 ma i/o digital operating current parallel interface @ 6.3fps 41.5 ma analog operating current parallel interface @ 6.3fps 101.0 ma pixel supply current parallel interface @ 6.3fps 2.5 ma pll supply current parallel interface @ 6.3fps 13.7 ma soft standby (clock on) mw table 28: absolute maximum ratings symbol definition condition min max unit v dd _max core digital voltage C0.3 1.9 v v dd _io_max i/o digital voltage C0.3 3.1 v v aa _max analog voltage C0.3 3.5 v v aa _pix pixel supply voltage C0.3 3.5 v v dd _pll pll supply voltage C0.3 3.5 v v dd _hispi_max hispi digital voltage C0.3 1.9 v v dd _tx_max hispi i/o digital voltage C0.3 1.9 v t st storage temperature C40 125 c
mt9f002 ds rev. h pub. 6/15 en 79 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics figure 67: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 29: two-wire serial register interface electrical characteristics f extclk = 24 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _hispi = 1.8v, v dd _tx = 0.4v; output load = 68.5pf; t j = 60c; data rate =660 mbps; dll set to 0 symbol parameter condition min typ max unit v il input low voltage C0.5 0.73 0.3 x v dd _io v i in input leakage current no pull up resistor; v in = v dd _io or d gnd C2 2 ? a v ol output low voltage at specified 2ma 0.031 0.032 0.035 v i ol output low current at specified v ol 0.1v 3 ma c in input pad capacitance 6 pf c load load capacitance pf s data s clk write start ack stop s data s clk read start ack tr_clk tf_clk 90% 10% tr_sdat tf_sdat 90% 10% t sdh t sds t shaw t ahsw t stps t stph register address bit 7 write address bit 0 register value bit 0 register value bit 7 read address bit 0 register value bit 0 write address bit 7 read address bit 7 t shar t sdsr t sdhr t ahsr t srth t sclk
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics mt9f002 ds rev. h pub. 6/15 en 80 ?semiconductor components industries, llc,2015. table 30: two-wire serial register interface timing specification f extclk = 24 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _hispi = 1.8v, v dd _tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 660 mbps,; dll set to 0 figure 68: i/o timing diagram symbol parameter condition min typ max unit f sclk serial interface input clock C 0 100 400 khz sclk duty cycle v od 45 50 60 % t rsclk/s data rise time 300 ? s t srts start setup time master write to slave 0.6 ? s t srth start hold time master write to slave 0.4 ? s t sdh s data hold master write to slave 0.3 0.65 ? s t sds s data setup master write to slave 0.3 ? s t shaw s data hold to ack master read to slave 0.15 0.65 ? s t ahsw ack hold to s data master write to slave 0.15 0.70 ? s t stps stop setup time master write to slave 0.3 ? s t stph stop hold time master write to slave 0.6 ? s t shar s data hold to ack master write to slave 0.3 1.65 ? s t ahsr ack hold to s data master write to slave 0.3 0.65 ? s t sdhr s data hold master read from slave .012 0.70 ? s t sdsr s data setup master read from slave 0.3 ? s data[11:0] frame_valid/ line_valid frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. pixclk extclk t cp t r t extclk t f t rp t fp t pd t pd t pfh t plh t pfl t pll pxl _0 pxl _1 pxl _2 pxl _n 90% 10% 90% 10%
mt9f002 ds rev. h pub. 6/15 en 81 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics slvs electrical specifications notes: 1. where 'n' is the number of phys 2. temperature of 25c table 31: i/o parameters f extclk = 24 mhz; v dd = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _hispi = 1.8v, v dd _tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 660 mbps,; dll set to 0 symbol definition conditions min max units v ih input high voltage v dd _io = 1.8v 1.4 v dd _io + 0.3 v v dd _io = 2.8v 2.4 v il input low voltage v dd _io = 1.8v gnd C 0.3 0.4 v dd _io = 2.8v gnd C 0.3 0.8 i in input leakage current no pull-up resistor; v in = v dd or d gnd C 20 20 ? a v oh output high voltage at specified i oh v dd _io - 0.4v C v v ol output low voltage at specified i ol C0.4v i oh output high current at specified v oh CC12ma i ol output low current at specified v ol C9ma i oz tri-state output leakage current C10 ? a table 32: i/o timing f extclk = 24 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _hispi = 1.8v, v dd _tx = 0.4v; output load = 68.5pf; t j = 60c; data rate = 660 mbps,; dll set to 0 symbol definition conditions min typ max units f extclk input clock frequency pll enabled 2 24 64 mhz t extclk input clock period pll enabled 200 41.7 15.6 ns t r input clock rise time 0.1 C 1 v/ns t f input clock fall time 0.1 C 1 v/ns clock duty cycle 45 50 55 % t jitter input clock jitter C C 0.3 ns output pin slew fastest c load = 15pf C 0.7 C v/ns f pixclk pixclk frequency default C C 96 mhz t pd pixclk to data valid default C C 3 ns t pfh pixclk to frame_valid high default C C 3 ns t plh pixclk to line_valid high default C C 3 ns t pfl pixclk to frame_valid low default C C 3 ns t pll pixclk to line_valid low default C C 3 ns table 33: power supply and operating temperature parameter symbol min typ max unit notes slvs current consumption i dd _tx n*18 ma 1, 2 hispi phy current consumption i dd _hispi n*45 ma 1, 2, 3 operating temperature t j -30 70 c 4
mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics mt9f002 ds rev. h pub. 6/15 en 82 ?semiconductor components industries, llc,2015. 3. up to 700 mbps 4. specification values may be exceeded when outside this temperature range. table 34: slvs electrical dc specification tj = 25c parameter symbol min typ max unit slvs dc mean common mode voltage v cm 0.45*v dd _t x 0.5*v dd _tx 0.55*v dd _tx v slvs dc mean differential output voltage |v od | 0.36*v dd _t x 0.5*v dd _tx 0.64*v dd _tx v change in v cm between logic 1 and 0 ? v cm 25 mv change in |v od | between logic 1 and 0 | v od |25mv v od noise margin nm 30 % difference in v cm between any two channels | ? v cm |50mv difference in v od between any two channels | ? v od |100mv common-mode ac voltage (pk) without vcm cap termination v cm_ac 50 mv common-mode ac voltage (pk) with vcm cap termination v cm_ac 30 mv maximum overshoot peak |v od |v od_ac 1.3*|v od |v maximum overshoot v diff pk-pk v diff_pkpk 2.6*v od v single-ended output impedance r o 35 50 70 ? output impedance mismatch ? r o 20 %
mt9f002 ds rev. h pub. 6/15 en 83 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics notes: 1. one ui is defined as the normalized mean ti me between one edge and the following edge of the clock. 2. taken from the 0v crossing point with the dll off. 3. also defined with a maximum loading capacitance of 10 pf on any pin. the loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute skew between any clock in one phy and any data lane in any other phy between any edges. differential skew is defined as the skew between co mplementary outputs. it is measured as the abso- lute time between the two complementary edges at mean v cm point. note that differential skew also is related to the ? vcm_ac spec which also must not be exceeded. hivcm electrical specifications the hispi 2.0 specification also defines an alternative signaling level mode called hivcm. both v od and v cm are still scalable with v dd _tx, but with v dd _tx nominal set to 1.8v the common-mode is elevated to around 0.9v. notes: 1. where 'n' is the number of phys 2. temperature of 25c 3. up to 700 mbps 4. specification values may be exceeded when outside this temperature range. table 35: slvs electrical timing specification parameter symbol min max unit notes data rate 1/ui 280 700 mbps 1 bitrate period t pw 1.43 3.57 ns 1 max setup time from transmitter t pre 0.3 ui 1, 2 max hold time from transmitter t post 0.3 ui 1, 2 eye width t eye 0.6 ui 1, 2 data total jitter (pk-pk) @1e-9 t totaljit 0.2 ui 1, 2 clock period jitter (rms) t ckjit 50 ps 2 clock cycle-to-cycle jitter (rms) t cycjit 100 ps 2 rise time (20% - 80%) tr 150ps 0.25 ui 3 fall time (20% - 80%) tf 150ps 0.25 ui 3 clock duty cycle dcyc 45 55 % 2 mean clock to data skew t chskew -0.1 0.1 ui 1, 4 phy-to-phy skew t physkew 2.1 ui 1, 5 mean differential skew t diffskew -100 100 ps 6 table 36: hivcm power supply and operating temperatures parameter symbol min typ max unit notes hivcm current consumption i dd _tx n*34 ma 1, 2 hispi phy current consumption i dd _hispi n*45 ma 1, 2, 3 operating temperature t j -30 70 c 4
mt9f002 ds rev. h pub. 6/15 en 84 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics table 37: hivcm electrical voltage and impedance specification tj = 25 c parameter symbol min typ max unit hivcm dc mean common mode voltage v cm 0.76 0.90 1.07 v hivcm dc mean differential output voltage |v od | 200 280 350 mv change in v cm between logic 1 and 0 ? v cm 25 mv change in |v od | between logic 1 and 0 | v od |25mv v od noise margin nm 30 % difference in v cm between any two channels | ? v cm |50mv difference in v od between any two channels | ? v od |100mv common-mode ac voltage (pk) without v cm cap termination ? v cm_ac 50 mv common-mode ac voltage (pk) with v cm cap termination ? v cm_ac 30 mv maximum overshoot peak |v od |v od_ac 1.3*|v od |v maximum overshoot vdiff pk-pk v diff_pkpk 2.6*v od v single-ended output impedance r o 40 70 100 ? output impedance mismatch ? r o 20 %
mt9f002 ds rev. h pub. 6/15 en 85 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics notes: 1. one ui is defined as the normalized mean ti me between one edge and the following edge of the clock. 2. taken from the 0 v crossing point with the dll off. 3. also defined with a maximum loading capacitance of 10pf on any pin. the loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute mean skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edges at mean v cm point. note that differential skew also is related to the ? vcm_ac spec which also must not be exceeded. electrical definitions figure 69 is the diagram defi ning differential amplitude v od , v cm, and rise and fall times. to measure v od and v cm use the dc test circuit shown in figure 70 on page 86 and set the hispi phy to constant logic 1 and logic 0. measure v oa , v ob and v cm with voltmeters for both logic 1 and logic 0. table 38: hivcm electrical ac specification parameter symbol min max unit notes data rate 1/ui 280 700 mbps 1 bitrate period t pw 1.43 3.57 ns 1 max setup time from transmitter t pre 0.3 ui 1, 2 max hold time from transmitter t post 0.3 ui 1, 2 eye width t eye 0.6 ui 1, 2 data total jitter (pk-pk) @1e-9 t totaljit 0.2 ui 1, 2 clock period jitter (rms) t ckjit 50 ps 2 clock cycle-to-cycle jitter (rms) t cycjit 100 ps 2 rise time (20% - 80%) t r 150ps 0.3 ui 3 fall time (20% - 80%) t f 150ps 0.3 ui 3 clock duty cycle d cyc 45 55 % 2 clock to data skew t chskew -0.1 0.1 ui 1, 4 phy-to-phy skew tp hyskew 2.1 ui 1, 5 mean differential skew t diffskew -100 100 ps 6
mt9f002 ds rev. h pub. 6/15 en 86 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics figure 69: single-ended and differential signals figure 70: dc test circuit v od (m)= |v oa (m)-v ob (m) | where 'm' is either ?1? for logic 1 or ?0? for logic 0 (eq 22) (eq 23) (eq 24) ? v od = |v od (1)-v od (0) | (eq 25) (eq 26) v oa v ob single- - ended signals differential signal v od = |v oa Cv ob | v od = |v ob Cv oa | v cm = (v oa + v ob )/2 v od 0v 80% 20% t r t f v od_ac v diff _pkpk v diff v v 50 50 v oa v ob v cm v od v od 1 ?? v od 0 ?? + 2 ----------------- -------------- ------------ - = v diff v od 1 ?? v od 0 ?? + = v cm v cm 1 ?? v cm 0 ?? + 2 --------------- ------------------ ----------- =
mt9f002 ds rev. h pub. 6/15 en 87 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics ? v cm = |v cm (1)-v cm (0) | (eq 27) both v od and v cm are measured for all output channels. the worst case ? v od is defined as the largest difference in v od between all channels regardless of logic level. and the worst case ? v cm is similarly defined as the largest difference in v cm between all chan- nels regardless of logic level. timing definitions 1. timing measurements are to be taken using the square wave test mode. 2. rise and fall times are measured between 20% to 80% positions on the differential waveform, as shown in figure 69: ?single-ended and differential signals,? on page 86. 3. mean clock-to-data skew should be measured from the 0v crossing point on clock to the 0v crossing point on any data channel regardless of edge, as shown in figure 71 on page 87. this time is compared with the ideal data transition point of 0.5ui with the difference being the clock-to-data skew (see equation 28 on page 87). figure 71: clock-to-data skew timing diagram (eq 28) (eq 29) 4. the differential skew is measured on the two single-ended signals for any channel. the time is taken from a transition on v oa signal to corresponding transition on v ob signal at v cm crossing point. t chskew ps ?? t ? t pw 2 ------ - ? = t chskew ui ?? t ? t pw ------ - 0.5 ? =
mt9f002 ds rev. h pub. 6/15 en 88 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics figure 72: differential skew figure 72 on page 88 also shows the corresponding ac v cm common-mode signal. differential skew between the v oa and v ob signals can cause spikes in the common- mode, which the receiver needs to be able to reject. v cm_ac is measured as the absolute peak deviation from the mean dc v cm common-mode. transmitter eye mask figure 73: transmitter eye mask figure 73 defines the eye mask for the transmitter. 0.5 ui point is the instantaneous crossing point of the clock. the area in white shows the area data is prohibited from crossing into. the eye mask also defines the minimum eye height, the data t pre and t post times, and the total jitter pk-pk +mean skew (t tjskew ) for data. ? t diffskew v cm v cm common-mode ac signal v cm_ac v cm_ac
mt9f002 ds rev. h pub. 6/15 en 89 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics clock signal t hclk is defined as the high clock period, and t lclk is defined as the low clock period as shown in figure 74. the clock duty cycle d cyc is defined as the percentage time the clock is either high (t hclk ) or low (t lclk ) compared with the clock period t. figure 74: clock duty cycle (eq 30) (eq 31) (i.e, 1 ui) (eq 32) (eq 33) figure 75 shows the definition of clock jitter for both the period and the cycle-to-cycle jitter. figure 75: clock jitter period jitter (t ckjit ) is defined as the deviation of the instantaneous clock t pw from an ideal 1ui. this should be measured for both the clock high period variation ? t hclk, and the clock low period variation ? t lclk taking the rms or 1-sigm a standard deviation and quoting the worse case jitter between ? t hclk and ? t lclk . d cyc 1 ?? t hclk t ------------- - = d cyc 0 ?? t lclk t ------------- = t pw t 2 -- - = bitrate 1 t pw ------ - =
mt9f002 ds rev. h pub. 6/15 en 90 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor electrical characteristics cycle-to-cycle jitter (t cycjit ) is defined as the difference in time between consecutive clock high and clock low periods t hclk and t lclk , quoting the rms value of the variation ? (t hclk - t lclk ). if pk-pk jitter is also measured, this should be limited to 3-sigma.
mt9f002 ds rev. h pub. 6/15 en 91 ?semiconductor components industries, llc,2015 mt9f002: 1/2.3-inch 14 mp cmos digital image sensor package dimensions package dimensions figure 76: 48-pin ilcc package outline drawing
mt9f002 ds rev. h pub. 6/15 en 92 ?semiconductor components industries, llc,2015. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor revision history revision history rev. h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/18/15 ? updated ?ordering information? on page 2 rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/15/15 ? updated ?ordering information? on page 2 rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/7/15 ? converted to on semiconductor template ? removed confidential marking rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/26/14 ? updated table 2, ?available part numbers,? on page 2 ? deleted figure 8: ?48-pin ilcc parallel package pinout diagram ? updated ?high speed serial pixel data interface? on page 15 ? updated ?power-on reset sequence? on page 34 ? updated figure 27: ?clocking configuration,? on page 37 ? updated ?summing mode? on page 49 ? updated corporate address on last page rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/29/12 ? updated trademarks rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/9/12 ? updated to production ? updated table 2, ?available part numbers,? on page 2 ? updated power consumption in table 1, ?key performance parameters,? on page 1 ? updated figure 5: ?typical configuratio n: serial four-lane hispi interface,? on page 10 ? updated figure 6: ?typical configuration: parallel pixel data interface,? on page 11 ? updated table 3, ?signal descriptions,? on page 13 ? updated figure 7: ?48-pin ilcc hispi package pinout diagram,? on page 14 ? updated figure 27: ?clocking configuration,? on page 37 ? updated ?power mode contexts? on page 54 ? updated paragraph under note to table 19, ?recommended register settings,? on page 56 and deleted old table 22, ?iso speed equivalent gain settings: rev. 3 sensor? ? updated figure 55: ?slave mode hispi ou tput (ers to grr transition),? on page 64 ? replaced figure 68: ?11.4 chief ray angle? with table 24, ?11.4 chief ray angle,? on page 76 ? updated table 27, ?dc electrical defi nitions and characteristics,? on page 78 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/14/11 ?changed v dd _slvs to v dd _hispi ?changed v dd _slvs_tx to v dd _tx ? updated to preliminary ? updated ?features? on page 1 ? updated table 2, ?available part numbers,? on page 2 ? updated table 1, ?key performance parameters,? on page 1 ? updated ?general description? on page 1 ? updated table 25, ?25 chief ray angle,? on page 77
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9f002: 1/2.3-inch 14 mp cmos digital image sensor revision history mt9f002 ds rev. h pub. 6/15 en 93 ?semiconductor components industries, llc,2015 . a-pix is a trademark of semiconductor components industries, llc (s cillc) or its subsidiaries in the united states and/or other countries. ? updated table 26, ?cra value,? on page 77 ? updated table 27, ?dc electrical defi nitions and characteristics,? on page 78 ? updated table 28, ?absolute maximum ratings,? on page 78 ? updated ?transmitter eye mask? on page 88 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/4/10 ?initial release

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